Patents by Inventor HSIANG YU

HSIANG YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12027422
    Abstract: A method for forming a semiconductor structure includes: forming an active layer on a substrate; forming hard masks on the active layer, wherein a first spacing is disposed between two closely spaced hard masks in a predetermined word line region nearest to a predetermined selective gate region, wherein the first spacing is less than a second spacing between any two of the hard masks other than the two closely spaced hard masks; forming spacers on the sidewalls of the hard masks, wherein two spacers on opposite sides of the sidewalls of the closely spaced hard masks merge into a combined spacer; and transferring the patterns of the spacers to the active layer to form word lines. The step of transferring the patterns of the spacers includes transferring the pattern of the combined spacer to the active layer to form a first word line.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: July 2, 2024
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Tseng-Yao Pan, Chien-Hsiang Yu, Hung-Sheng Chen, Ching-Yung Wang, Cheng-Hong Wei
  • Publication number: 20240207499
    Abstract: A patient monitoring system may be used with catheters to monitor the infusion and drainage of any solution into the human body. The system may be used, for example, with in-dwelling catheters for peritoneal dialysis in end stage renal disease (ESRD) patients, urinary tract catheters, insulin pumps in diabetic patients, feeding tubes and central venous line catheters. The patient monitoring system includes one or more fluid pathways for infusing into and/or draining solutions out of the catheter, and one or more sensors to monitor the fluid. The patient monitoring system transmits the patient monitoring data to a database, allowing data storage, processing, and access through graphical user interfaces to patients and providers via device applications or browser-based web access portals.
    Type: Application
    Filed: January 5, 2024
    Publication date: June 27, 2024
    Inventors: Aly R. ELBADRY, Eric Hsiang YU, Ahmad Naim SALEH, Michael Austin SNYDER
  • Patent number: 12021812
    Abstract: Methods and systems are provided for facilitating time zone prediction using electronic communication data. Electronic message data associated with a message recipient of electronic communications is obtained. The electronic message data includes message delivery data associated with an electronic message and message response data associated with a response, by the message recipient, to a received electronic message. Using a machine learning model and based on the message delivery data and the message response data, a time-zone score is determined for a time zone. Such a time-zone score can indicate a probability the time zone corresponds with the message recipient. Based on the time-zone score, the time zone is identified as corresponding with the message recipient.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: June 25, 2024
    Assignee: Adobe Inc.
    Inventors: Lijun Yu, Wuyang Dai, Jun He, Hsiang-Yu Yang, Zhenyu Yan
  • Publication number: 20240196091
    Abstract: An image capturing device is provided. An image sensor is configured to capture an image of a target at a predetermined time interval according to a target exposure setting, to provide a series of preview frames at a frame rate. A storage device is configured to store each of the preview frames. A processor is configured to access the storage device to obtain first and second preview frames, determine a motion value of the target according to the first and second preview frames, and update the target exposure setting according to the motion value of the target. The image sensor is configured to capture the image of the target according to the updated target exposure setting to provide next preview frame.
    Type: Application
    Filed: April 25, 2023
    Publication date: June 13, 2024
    Inventors: Bo-Ying CHEN, Ping-Hsien LEE, Chih-Hsiang YU
  • Patent number: 11992343
    Abstract: Devices, systems, and methods herein relate to predicting infection of a patient. These systems and methods may comprise illuminating a patient fluid in a fluid conduit from a plurality of illumination directions, measuring an optical characteristic of the illuminated patient fluid using one or more sensors, and predicting an infection state of the patient based at least in part on the measured optical characteristic.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: May 28, 2024
    Assignee: GASTROKLENZ INC.
    Inventors: Eric Hsiang Yu, Aly R. Elbadry, Carlos Rovira Borras, Daniel Elliott Francis
  • Publication number: 20240168751
    Abstract: In implementations of systems for estimating temporal occurrence of a binary state change, a computing device implements an occurrence system to compute a posterior probability distribution for temporal occurrences of binary state changes associated with client computing devices included in a group of client computing devices. The occurrence system determines probabilities of a binary state change associated with a client computing device included in the group of client computing devices based on the posterior probability distribution, and the probabilities correspond to future periods of time. A future period of time is identified based on a probability of the binary state change associated with the client computing device. The occurrence system generates a communication based on a communications protocol for transmission to the client computing device via a network at a period of time that correspond to the future period of time.
    Type: Application
    Filed: November 17, 2022
    Publication date: May 23, 2024
    Applicant: Adobe Inc.
    Inventors: Luwan Zhang, Zhenyu Yan, Jun He, Hsiang-yu Yang, Cheng Zhong
  • Publication number: 20240160185
    Abstract: The invention provides a portable CNC machine, including a body and four anchorage bases. The body is put on a surface of a work frame. The body is provided with a machining tool, a processing module and four take-up and pay-off modules, each take-up and pay-off module takes up and pays off a cable, a tail end of each cable is provided with an anchor, and the processing module is connected to and controls the four take-up and pay-off modules. The four anchorage bases are disposed at four corners of the work frame respectively, and stretch and hang the four anchors thereon respectively. The processing module controls the four take-up and pay-off modules to take up and pay off the cables to control the body to freely move on the work frame, and at the same time, the processing module controls the machining tool to carry out a machining operation.
    Type: Application
    Filed: September 27, 2023
    Publication date: May 16, 2024
    Inventors: Ren-Yu Yeh, Po-Hsiang Yu, Chih-Wen Cheng
  • Publication number: 20240160928
    Abstract: A method for enhancing kernel reparameterization of a non-linear machine learning model includes providing a predefined machine learning model, expanding a kernel of the predefined machine learning model with a non-linear network for convolution operation of the predefined machine learning model to generate the non-linear machine learning model, training the non-linear machine learning model, reparameterizing the non-linear network back to a kernel for convolution operation of the non-linear machine learning model to generate a reparameterized machine learning model, and deploying the reparameterized machine learning model to an edge device.
    Type: Application
    Filed: November 10, 2023
    Publication date: May 16, 2024
    Applicant: MEDIATEK INC.
    Inventors: Po-Hsiang Yu, Hao Chen, Cheng-Yu Yang, Peng-Wen Chen
  • Publication number: 20240160919
    Abstract: In aspects of the disclosure, a method, a system, and a computer-readable medium are provided. The method of building a kernel reparameterization for replacing a convolution-wise operation kernel in training of a neural network comprises selecting one or more blocks from tensor blocks and operations; and connecting the selected one or more blocks with the selected operations to build the kernel reparameterization. The kernel reparameterization has a dimension same as that of the convolution-wise operation kernel.
    Type: Application
    Filed: October 17, 2023
    Publication date: May 16, 2024
    Inventors: Po-Hsiang Yu, Hao Chen, Peng-Wen Chen, Cheng-Yu Yang
  • Publication number: 20240160934
    Abstract: A method for removing branches from trained deep learning models is provided. The method includes steps (i)-(v). In step (i), a trained model is obtained. The trained model has a branch structure involving one or more original convolutional layers and a shortcut connection. In step (ii), the shortcut connection is removed from the branch structure. In step (iii), a reparameterization model is built by linearly expanding each of the original convolutional layers into a reparameterization block in the reparameterization model. In step (iv), parameters of the reparameterization blocks are optimized by training the reparameterization model. In step (v), each of the optimized reparameterization blocks is transformed into a reparameterized convolutional layer to form a branchless structure that replaces the branch structure in the trained model.
    Type: Application
    Filed: August 16, 2023
    Publication date: May 16, 2024
    Inventors: Hao CHEN, Po-Hsiang YU, Yu-Cheng LO, Cheng-Yu YANG, Peng-Wen CHEN
  • Publication number: 20240161013
    Abstract: A reparameterization method for initializing a machine learning model includes initializing a prefix layer of a first low dimensional layer in the machine learning model and a postfix layer of the first low dimensional layer, inverting the prefix layer to generate an inverse prefix layer of the first low dimensional layer, inverting the postfix layer to generate an inverse postfix layer of the first low dimensional layer, combining the inverse prefix layer, the first low dimensional layer and the inverse postfix layer to form a high dimensional layer, generating parallel operation layers from the high dimensional layer, and assigning initial weights to the parallel operation layers.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 16, 2024
    Applicant: MEDIATEK INC.
    Inventors: Cheng-Yu Yang, Hao Chen, Po-Hsiang Yu, Peng-Wen Chen
  • Patent number: 11978768
    Abstract: A method manufacturing of a semiconductor structure including following steps is provided. A material layer is provided. A first mask layer is formed on the material layer. Core patterns are formed on the first mask layer. A spacer material layer is conformally formed on the core patterns. An etch-back process is performed on the spacer material layer. A portion of the spacer material layer located on two ends of the core pattern is removed, then spacer structures are formed. Each spacer structure includes a merged spacer and a non-merged spacer. The core patterns are removed. The first patterned mask layer is formed to cover a portion of the merged spacer and expose another portion of the merged spacer and the non-merged spacer. The first patterned mask layer and the spacer structure are used as a mask, and the first mask layer is patterned into a second patterned mask layer.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: May 7, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Tseng-Yao Pan, Chien-Hsiang Yu, Ching-Yung Wang, Cheng-Hong Wei, Ming-Tsang Wang
  • Patent number: 11971824
    Abstract: Disclosed is a method for enhancing memory utilization and throughput of a computing platform in training a deep neural network (DNN). The critical features of the method includes: calculating a memory size for every operation in a computational graph, storing the operations in the computational graph in multiple groups with the operations in each group being executable in parallel and a total memory size less than a memory threshold of a computational device, sequentially selecting a group and updating a prefetched group buffer, and simultaneously executing the group and prefetching data for a group in the prefetched group buffer to the corresponding computational device when the prefetched group buffer is update. Because of group execution and data prefetch, the memory utilization is optimized and the throughput is significantly increased to eliminate issues of out-of-memory and thrashing.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: April 30, 2024
    Assignee: AETHERAI IP HOLDING LLC
    Inventors: Chi-Chung Chen, Wei-Hsiang Yu, Chao-Yuan Yeh
  • Publication number: 20240134538
    Abstract: A memory operation method, comprising: when a first super block of a memory device is a open block (or in programming state), obtaining a first read count of one of a plurality of first memory blocks in the first super block, wherein the first read count is a number of times that data of one of the first memory blocks is read out; determining whether the first read count is larger than a first threshold; and when the first read count is larger than the first threshold, moving a part of the data in the first super block to a safe area in the memory device, wherein the part of the data comprises data in the first memory block.
    Type: Application
    Filed: June 5, 2023
    Publication date: April 25, 2024
    Inventors: Po-Sheng CHOU, Hsiang-Yu HUANG, Yan-Wen WANG
  • Publication number: 20240104019
    Abstract: Disclosed is a method for enhancing memory utilization and throughput of a computing platform in training a deep neural network (DNN). The critical features of the method includes: calculating a memory size for every operation in a computational graph, storing the operations in the computational graph in multiple groups with the operations in each group being executable in parallel and a total memory size less than a memory threshold of a computational device, sequentially selecting a group and updating a prefetched group buffer, and simultaneously executing the group and prefetching data for a group in the prefetched group buffer to the corresponding computational device when the prefetched group buffer is update. Because of group execution and data prefetch, the memory utilization is optimized and the throughput is significantly increased to eliminate issues of out-of-memory and thrashing.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 28, 2024
    Applicant: AETHERAI IP HOLDING LLC
    Inventors: Chi-Chung CHEN, Wei-Hsiang YU, Chao-Yuan YEH
  • Patent number: 11926678
    Abstract: Disclosed herein are composite polypeptide. According to various embodiments, the composite polypeptide includes a parent polypeptide and a metal binding motif capable of forming a complex with a metal cation. The composite polypeptide may be conjugated with a linker unit having a plurality of functional elements to form a multi-functional molecular construct. Alternatively, multiple composite polypeptides may be conjugated to a linker unit to form a molecular construct, or a polypeptide bundle. Linker units suitable for conjugating with the composite polypeptide having the metal binding motif are also disclosed.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: March 12, 2024
    Assignee: Immunwork Inc.
    Inventors: Tse-Wen Chang, Hsing-Mao Chu, Wei-Ting Tian, Yueh-Hsiang Yu
  • Publication number: 20240074761
    Abstract: An implantable rotator cuff muscle suture spacer with pressure sensing is provided, formed by a semiconductor manufacture procedure, including a base layer, made of a polymer material and having flexibility, and further including a first configuration region and a second configuration region, where the base layer is folded at imaginary fold line positions of the first configuration region and the second configuration region, so that the first configuration region is located above the second configuration region; a first electrode region, deposited on the first configuration region; a second electrode region, deposited on the second configuration region, corresponding to a position below the first electrode region, and configured to obtain a pressure sensing value; an inductance coil, deposited on the second configuration region and surrounding the second electrode region; and a capacitor layer, coated above a surface of the base layer to form a dielectric substance.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 7, 2024
    Inventors: WEN CHENG KUO, HSIANG-YU WU, SONG-CHENG HONG
  • Publication number: 20240063294
    Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a plurality of dummy gates over a substrate and performing a first etch step and a second etch step on the substrate exposed between the dummy gates. The first etch step includes an anisotropic etching process and an isotropic etching process. The second includes an isotropic etching step.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Inventors: Ta-Chun LIN, Jyun-Yang SHEN, Hsiang-Yu LAI, Shih-Chang TSAI, Chun-Jun LIN, Kuo-Hua PAN, Jhon Jhy LIAW
  • Publication number: 20240046966
    Abstract: A three-dimensional (3D) NAND memory structure may include material layers arranged in a vertical stack including alternating horizontal insulating layers and wordline layers. The material layers may be etched to form a landing pad. A vertical wordline may extend through one or more of the horizontal wordline layers beneath the landing pad. The vertical wordline may be conductively connected to a top horizontal wordline, and the vertical wordline may be insulated from any of the horizontal wordlines that the vertical wordline extends through beneath the top horizontal wordline. A liner may also be formed over a top horizontal wordline at the landing pad.
    Type: Application
    Filed: August 8, 2023
    Publication date: February 8, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Hsiang Yu Lee, Pradeep K. Subrahmanyan, Takaya Matsushita, Changwoo Sun
  • Patent number: 11875058
    Abstract: A control method for a multi-channel non-volatile memory is shown. When reading a read target on the non-volatile memory, the controller increases the read count of the monitored unit to which the read target belongs and, based on the read count, determines whether to move data of the monitored unit covering the read target to a safe space to deal with reading interference. The monitored unit is smaller than a cross-channel management unit in read-count group. The controller accesses a parallel accessing space of the non-volatile memory in parallel through all of the channels, and allocates the parallel accessing space based on the cross-channel management unit.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: January 16, 2024
    Assignee: Silicon Motion, Inc.
    Inventors: Po-Sheng Chou, Hsiang-Yu Huang