Patents by Inventor Hsiao-Wen Lee

Hsiao-Wen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563105
    Abstract: A semiconductor device includes a gate structure extending along a first lateral direction. The semiconductor device includes a source/drain structure disposed on one side of the gate structure along a second lateral direction, the second lateral direction perpendicular to the first lateral direction. The semiconductor device includes an air gap disposed between the gate structure and the source/drain structure along the second lateral direction, wherein the air gap is disposed over the source/drain structure.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Chao-Cheng Chen
  • Publication number: 20230016605
    Abstract: A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.
    Type: Application
    Filed: July 15, 2021
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Chia-Hao Yu, Hsiao Wen Lee
  • Patent number: 11552195
    Abstract: A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Li-Jung Kuo, Chen-Ping Chen, Ming-Ching Chang
  • Publication number: 20220393018
    Abstract: A semiconductor device is described. An isolation region is disposed on the substrate. A plurality of channels extend through the isolation region from the substrate. The channels including an active channel and an inactive channel. A dummy fin is disposed on the isolation region and between the active channel and the inactive channel. An active gate is disposed over the active channel and the inactive channel, and contacts the isolation region. A dielectric material extends through the active gate and contacts a top of the dummy fin. The inactive channel is a closest inactive channel to the dielectric material. A long axis of the active channel extends in a first direction. A long axis of the active gate extends in a second direction. The active channel extends in a third direction from the substrate. The dielectric material is closer to the inactive channel than to the active channel.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao LIN, Hsiao Wen Lee, Ya-Yi Tsai, Shu-Uei Jang, Chih-Han Lin, Shu-Yuan Ku
  • Patent number: 11522073
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUTOR MANUFACTURING COMPANY LIMITED
    Inventors: Shih-Yao Lin, Chih-Han Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee
  • Publication number: 20220384356
    Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Inventors: Han-Ping PU, Hsiao-Wen LEE
  • Publication number: 20220367672
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao LIN, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee, Chih-Han Lin
  • Publication number: 20220352031
    Abstract: A semiconductor device may be formed by forming a first fin and a second fin in a first area and a second area of a substrate, respectively; which may be followed by forming of a first dummy gate structure and a second dummy gate structure straddling the first fin and second fin, respectively and forming a sacrificial layer extending along a bottom portion of the second dummy gate structure. The first dummy gate structure may be replaced with a first metal gate structure, while the second dummy gate structure and the sacrificial layer may be replaced with a second metal gate structure.
    Type: Application
    Filed: April 30, 2021
    Publication date: November 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Chih-Han Lin
  • Publication number: 20220336625
    Abstract: A semiconductor device includes a gate structure extending along a first lateral direction. The semiconductor device includes a source/drain structure disposed on one side of the gate structure along a second lateral direction, the second lateral direction perpendicular to the first lateral direction. The semiconductor device includes an air gap disposed between the gate structure and the source/drain structure along the second lateral direction, wherein the air gap is disposed over the source/drain structure.
    Type: Application
    Filed: April 14, 2021
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Chao-Cheng Chen
  • Publication number: 20220336662
    Abstract: A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.
    Type: Application
    Filed: April 14, 2021
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Li-Jung Kuo, Chen-Ping Chen, Ming-Ching Chang
  • Publication number: 20220328309
    Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
  • Publication number: 20220310819
    Abstract: A semiconductor device includes a channel structure, extending along a first lateral direction, that is disposed over a substrate. The semiconductor device includes a gate structure, extending along a second lateral direction perpendicular to the first lateral direction, that straddles the channel structure. The semiconductor device includes an epitaxial structure, coupled to the channel structure, that is disposed next to the gate structure. The semiconductor device includes a first gate spacer and a second gate spacer each comprising a first portion disposed between the gate structure and the epitaxial structure along the first lateral direction. The semiconductor device includes an air gap interposed between the first portion of the first gate spacer and the first portion of the second gate spacer. The air gap exposes a second portion of the first gate spacer that extends in the first lateral direction.
    Type: Application
    Filed: October 4, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Ming-Ching Chang
  • Publication number: 20220302276
    Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chih-Han Lin, Hsiao Wen Lee
  • Publication number: 20220293594
    Abstract: A semiconductor device includes a dielectric fin between a first semiconductor channel and a second semiconductor channel. The semiconductor device includes a first gate structure. The first gate structure includes a first portion and a second portion separated from each other by the dielectric fin. The semiconductor device includes a first gate spacer that extends along sidewalls of the first portion of the first gate structure. The semiconductor device includes a second gate spacer that extends along sidewalls of the second portion of the first gate structure, respectively. At least one of the first gate spacer or second gate spacer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness, and wherein the first portion is closer to the dielectric fin than the second portion.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chieh-Ning Feng, Hsiao Wen Lee, Chao-Cheng Chen
  • Patent number: 11437327
    Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Ping Pu, Hsiao-Wen Lee
  • Publication number: 20220246579
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Publication number: 20220223587
    Abstract: A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.
    Type: Application
    Filed: January 11, 2021
    Publication date: July 14, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Ming-Ching Chang
  • Patent number: 11387341
    Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Chih-Han Lin, Hsiao Wen Lee
  • Patent number: 11380542
    Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
  • Patent number: 11342306
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Grant
    Filed: August 30, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee