Patents by Inventor Hsiao-Wen Lee
Hsiao-Wen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220310819Abstract: A semiconductor device includes a channel structure, extending along a first lateral direction, that is disposed over a substrate. The semiconductor device includes a gate structure, extending along a second lateral direction perpendicular to the first lateral direction, that straddles the channel structure. The semiconductor device includes an epitaxial structure, coupled to the channel structure, that is disposed next to the gate structure. The semiconductor device includes a first gate spacer and a second gate spacer each comprising a first portion disposed between the gate structure and the epitaxial structure along the first lateral direction. The semiconductor device includes an air gap interposed between the first portion of the first gate spacer and the first portion of the second gate spacer. The air gap exposes a second portion of the first gate spacer that extends in the first lateral direction.Type: ApplicationFiled: October 4, 2021Publication date: September 29, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Ming-Ching Chang
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Publication number: 20220302276Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.Type: ApplicationFiled: June 7, 2022Publication date: September 22, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chih-Han Lin, Hsiao Wen Lee
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Publication number: 20220293594Abstract: A semiconductor device includes a dielectric fin between a first semiconductor channel and a second semiconductor channel. The semiconductor device includes a first gate structure. The first gate structure includes a first portion and a second portion separated from each other by the dielectric fin. The semiconductor device includes a first gate spacer that extends along sidewalls of the first portion of the first gate structure. The semiconductor device includes a second gate spacer that extends along sidewalls of the second portion of the first gate structure, respectively. At least one of the first gate spacer or second gate spacer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness, and wherein the first portion is closer to the dielectric fin than the second portion.Type: ApplicationFiled: March 12, 2021Publication date: September 15, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chieh-Ning Feng, Hsiao Wen Lee, Chao-Cheng Chen
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Patent number: 11437327Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.Type: GrantFiled: December 15, 2020Date of Patent: September 6, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Ping Pu, Hsiao-Wen Lee
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Publication number: 20220246579Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.Type: ApplicationFiled: April 22, 2022Publication date: August 4, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
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Publication number: 20220223587Abstract: A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.Type: ApplicationFiled: January 11, 2021Publication date: July 14, 2022Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Ming-Ching Chang
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Patent number: 11387341Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.Type: GrantFiled: September 29, 2020Date of Patent: July 12, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Yao Lin, Chih-Han Lin, Hsiao Wen Lee
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Patent number: 11342306Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.Type: GrantFiled: August 30, 2020Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
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Publication number: 20220130978Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.Type: ApplicationFiled: October 27, 2020Publication date: April 28, 2022Inventors: Shih-Yao Lin, Chih-Han Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee
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Publication number: 20220130977Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a fin layer. Dummy gates are formed over the fin layer, where the dummy gates are formed to taper from a smaller width at a top region of the dummy gates to a larger width at a bottom region of the dummy gates. Sidewall spacers are formed on sidewalls of the dummy gates. An interlayer dielectric is formed in regions between the dummy gates and contacts the sidewall spacers. The dummy gates are removed to form openings in the interlayer dielectric and to expose the sidewall spacers on sides of the openings in the interlayer dielectric. The sidewall spacers are etched at a greater rate at a top region of the sidewall spacers than at a bottom region of the sidewall spacers.Type: ApplicationFiled: October 27, 2020Publication date: April 28, 2022Inventors: Shih-Yao Lin, Chih-Han Lin, Hsiao Wen Lee
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Publication number: 20220102519Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.Type: ApplicationFiled: September 29, 2020Publication date: March 31, 2022Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Yao Lin, Chih-Han Lin, Hsiao Wen Lee
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Patent number: 11189596Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.Type: GrantFiled: July 14, 2020Date of Patent: November 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
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Publication number: 20210335728Abstract: Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector and the semiconductor substrate and covering the adhesive layer. An interface between the adhesive layer and the first buffer layer is substantially level with a bottom surface of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.Type: ApplicationFiled: July 2, 2021Publication date: October 28, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Wen LEE, Hsien-Wen LIU, Shin-Puu JENG
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Patent number: 11056445Abstract: Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The first buffer layer is sandwiched between the encapsulation layer and the semiconductor substrate, and a sidewall of the encapsulation layer is in direct contact with a sidewall of the first buffer layer and a sidewall of the adhesive layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.Type: GrantFiled: December 31, 2019Date of Patent: July 6, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiao-Wen Lee, Hsien-Wen Liu, Shin-Puu Jeng
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Patent number: 11050868Abstract: An internet phone system includes an internet phone main body, an expansion device and a multiple-layer connecting card. The internet phone main body includes a first connecting port. The at least one expansion device includes a second connecting port. One end of the multiple-layer connecting card is connected to the first connecting port, and the other end is connected to the second connecting port such that the internet phone main body can be electrically connected to the expansion device via the multiple-layer connecting card. The expansion device is capable of combining with another expansion device by another multiple-layer connecting card.Type: GrantFiled: June 24, 2019Date of Patent: June 29, 2021Assignee: Pegatron CorporationInventors: Yu-Ti Kuo, Wen-Hsieh Hsieh, Chao-Tang Chiu, Chien-Yi Lee, Hsiao-Wen Lee, Ching-Jen Wang
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Publication number: 20210098385Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.Type: ApplicationFiled: December 15, 2020Publication date: April 1, 2021Inventors: Han-Ping Pu, Hsiao-Wen Lee
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Patent number: 10890837Abstract: A structured light projection system including a substrate, a semiconductor laser chip, a first optical module, and a second optical module is provided. The semiconductor laser chip is electrically connected to the substrate. The first optical module is disposed on the substrate. The second optical module is disposed on the first optical module. The deviation rate between optical axes of the optical modules and the semiconductor laser chip and the calibration time thereof are reduced by the first optical module directly packaging the substrate through a primary optics design, so as to increase the yield of the structured light projection.Type: GrantFiled: April 16, 2019Date of Patent: January 12, 2021Assignee: LIGITEK ELECTRONICS CO., LTD.Inventors: Hsiao-Wen Lee, I-Hsin Tung
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Publication number: 20200395335Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.Type: ApplicationFiled: August 30, 2020Publication date: December 17, 2020Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
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Patent number: 10867930Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.Type: GrantFiled: April 8, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Ping Pu, Hsiao-Wen Lee
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Publication number: 20200343220Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.Type: ApplicationFiled: July 14, 2020Publication date: October 29, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee