Abstract: A semiconductor device may be formed by forming a first fin and a second fin in a first area and a second area of a substrate, respectively; which may be followed by forming of a first dummy gate structure and a second dummy gate structure straddling the first fin and second fin, respectively and forming a sacrificial layer extending along a bottom portion of the second dummy gate structure. The first dummy gate structure may be replaced with a first metal gate structure, while the second dummy gate structure and the sacrificial layer may be replaced with a second metal gate structure.

Abstract: A method for making a semiconductor device includes forming a fin structure that extends along a first direction and comprises a plurality of sacrificial layers and a plurality of channel layers alternately stacked on top of one another, forming a dummy gate structure over the fin structure and extending along a second direction perpendicular to the first direction, and forming a gate spacer. The gate spacer extends in the second direction along respective upper sidewall portions of the dummy gate structure and is separated by a portion of the dummy gate structure from a topmost one of the plurality of channel layers, such that a first distance between a bottom surface of the gate spacer and a top surface of the topmost one of the plurality of channel layers is defined by the portion of the dummy gate structure.

Abstract: A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

Abstract: A semiconductor device includes a plurality of channel layers vertically spaced from one another, a gate structure wrapping around each of the plurality of channel layers; and an inner spacer that is disposed along sidewalls of a lower portion of the gate structure. The inner spacer curves toward the lower portion of the gate structure.

Abstract: A semiconductor device includes a dielectric fin between a first semiconductor channel and a second semiconductor channel. The semiconductor device includes a first gate structure. The first gate structure includes a first portion and a second portion separated from each other by the dielectric fin. The semiconductor device includes a first gate spacer that extends along sidewalls of the first portion of the first gate structure. The semiconductor device includes a second gate spacer that extends along sidewalls of the second portion of the first gate structure, respectively. At least one of the first gate spacer or second gate spacer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness, and wherein the first portion is closer to the dielectric fin than the second portion.

Abstract: A method includes forming a dielectric fin over a substrate between a first semiconductor fin and a second semiconductor fin. The first and second semiconductor fins, and the dielectric fin all extend along a first lateral direction. The method includes forming a dummy gate structure that extends along a second lateral direction and includes a first portion and a second portion. The first and second portions overlay the first and second semiconductor fins, respectively, and separate from each other with the dielectric fin. The method includes removing upper sidewall portions of the dielectric fin. The method includes replacing the first and second portions of the dummy gate structure with a first and second active gate structures, respectively.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a fin layer. Dummy gates are formed over the fin layer, where the dummy gates are formed to taper from a smaller width at a top region of the dummy gates to a larger width at a bottom region of the dummy gates. Sidewall spacers are formed on sidewalls of the dummy gates. An interlayer dielectric is formed in regions between the dummy gates and contacts the sidewall spacers. The dummy gates are removed to form openings in the interlayer dielectric and to expose the sidewall spacers on sides of the openings in the interlayer dielectric. The sidewall spacers are etched at a greater rate at a top region of the sidewall spacers than at a bottom region of the sidewall spacers.

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

Abstract: A method for making a semiconductor device includes: forming a first through sixth fin structures over a substrate, all extending along a first lateral direction, the second fin structure separated from each of the first and third fin structures with a first distance, the fifth fin structure separated from each of the fourth and sixth fin structures with the first distance, and the third fin structure separated from the fourth fin structure with a second distance; forming gate structures overlaying a respective portion of each of the first through sixth fin structures; forming a first through sixth pairs of trenches by removing respective portions of each of the first through sixth fin structures not overlaid by the gate structures; forming a dielectric passivation layer over the third and fourth pairs of trenches; and growing source/drain structures in the first, second, fifth, and sixth pairs of trenches, respectively.

Abstract: A method for making a semiconductor device includes forming a fin structure that extends along a first direction and comprises a plurality of sacrificial layers and a plurality of channel layers alternately stacked on top of one another. The method includes forming a dummy gate structure, over the fin structure, that extends along a second direction perpendicular to the first direction. The method includes forming a gate spacer extending along respective upper sidewall portions of the dummy gate structure, thereby defining a first distance between a bottom surface of the gate spacer and a top surface of a topmost one of the plurality of channel layers. The first distance is either zero or similar to a second distance that separates neighboring ones of the plurality of channel layers.

Abstract: A semiconductor device may be formed by forming a first fin and a second fin in a first area and a second area of a substrate, respectively; which may be followed by forming of a first dummy gate structure and a second dummy gate structure straddling the first fin and second fin, respectively and forming a sacrificial layer extending along a bottom portion of the second dummy gate structure. The first dummy gate structure may be replaced with a first metal gate structure, while the second dummy gate structure and the sacrificial layer may be replaced with a second metal gate structure.

Abstract: A semiconductor device includes a plurality of channel layers vertically spaced from one another. The semiconductor device includes a gate structure wrapping around each of the plurality of channel layers. The semiconductor device includes an epitaxial structure electrically coupled to the plurality of channel layers. The epitaxial structure contacts a sidewall, a portion of a top surface, and a portion of a bottom surface of each of the plurality of channel layers.

Abstract: A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

Abstract: A semiconductor device includes a dielectric fin between a first semiconductor channel and a second semiconductor channel. The semiconductor device includes a first gate structure. The first gate structure includes a first portion and a second portion separated from each other by the dielectric fin. The semiconductor device includes a first gate spacer that extends along sidewalls of the first portion of the first gate structure. The semiconductor device includes a second gate spacer that extends along sidewalls of the second portion of the first gate structure. At least one of the first gate spacer or second gate spacer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness, and wherein the first portion is closer to the dielectric fin than the second portion.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

Abstract: A semiconductor device includes a gate structure extending along a first lateral direction. The semiconductor device includes a source/drain structure disposed on one side of the gate structure along a second lateral direction, the second lateral direction perpendicular to the first lateral direction. The semiconductor device includes an air gap disposed between the gate structure and the source/drain structure along the second lateral direction, wherein the air gap is disposed over the source/drain structure.

Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

Abstract: A semiconductor device is described. An isolation region is disposed on the substrate. A plurality of channels extend through the isolation region from the substrate. The channels including an active channel and an inactive channel. A dummy fin is disposed on the isolation region and between the active channel and the inactive channel. An active gate is disposed over the active channel and the inactive channel, and contacts the isolation region. A dielectric material extends through the active gate and contacts a top of the dummy fin. The inactive channel is a closest inactive channel to the dielectric material. A long axis of the active channel extends in a first direction. A long axis of the active gate extends in a second direction. The active channel extends in a third direction from the substrate. The dielectric material is closer to the inactive channel than to the active channel.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.