Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.

Abstract: A semiconductor device is described. An isolation region is disposed on the substrate. A plurality of channels extend through the isolation region from the substrate. The channels including an active channel and an inactive channel. A dummy fin is disposed on the isolation region and between the active channel and the inactive channel. An active gate is disposed over the active channel and the inactive channel, and contacts the isolation region. A dielectric material extends through the active gate and contacts a top of the dummy fin. The inactive channel is a closest inactive channel to the dielectric material. A long axis of the active channel extends in a first direction. A long axis of the active gate extends in a second direction. The active channel extends in a third direction from the substrate. The dielectric material is closer to the inactive channel than to the active channel.

Abstract: A foot sensor and analysis device, which includes a pressure sensing layer arranged inside the insole and a sensing module installed inside the insole. The sensing module is electrically coupled with the pressure sensing layer for receiving and processing detected electronic signals, where sensing module includes an inductance coil to perform wireless charging to the battery. The pressure sensing layer and the sensing module are integrally formed inside the insole.

Abstract: A wearable heart sound detection system, which includes an acoustic sensing device for collecting heart sound signals of the body, performing signal amplification, filtering, digitization and other preprocessing on the collected heart sound signals, and outputting the preprocessed heart sound signals; a computing electronic device communicatively coupled to the acoustic sensing device for acquiring the preprocessed heart sound signal, and a cloud data database communicatively coupled to the external computing electronic device. The acoustic device includes a capacitive sound sensor, a piezoelectric sound sensor and a circuit assembly. The circuit assembly is respectively electrically connected with the capacitive sound sensor and the piezoelectric sound sensor. The circuit assembly, the capacitive sound sensor and the piezoelectric sound sensor are integrated on a flexible substrate.

Abstract: The present invention discloses a smart noise reduction device including a control device; an audio waveform pattern recognizer coupled to the control device for identifying an audio mixed signal including a regularity signal and a non-regularity signal; an audio waveform pattern database coupled to the control device, including at least one audio type, each having a plurality of preset second regularity signals; and an audio filter coupled to the control device to obtain the regularity signal.

Abstract: The present invention discloses a method of noise reduction for an intelligent network communication, which includes the following steps: first, receiving a local sound message through a sound receiver of a communication device at the transmitting end. Next, a voice recognizer is used to identify the voice characteristics of the speaker; then, it is determined from a voice database whether there is a corresponding or similar voice characteristic of the speaker recognized by the voice recognizer. Finally, filtering other signals other than the voice characteristic signal of the speaker through a sound filter to obtain the original sound emitted by the speaker.

Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.

Abstract: A hybrid diaphragm structure is provided. The hybrid diaphragm structure includes a substrate, a first diaphragm disposed in a central region of the substrate, a first coil structure disposed over the first diaphragm, a first groove separating the first diaphragm and the first coil structure from the substrate, and a first bridge structure coupling the first diaphragm to the substrate. The first diaphragm and the substrate include a same material.

Abstract: A data protection method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes, and the plurality of disk array tags corresponding to one of the word lines connected to one of the memory planes are at least partially identical to the plurality of disk array tags corresponding to another one of the word lines connected to another one of the memory planes; receiving a write command and data corresponding to the write command from a host system; and sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.

Abstract: An active sounding device integrated into a flat panel display includes a glass diaphragm having a first surface on which a light emitting array and a touch panel are formed, a plurality of planar voice coils arranged on the second surface of the glass diaphragm opposite to the first surface, and a magnet assembly arranged below the plurality of planar voice coils, wherein the plurality of planar voice coils are electromagnetically coupled to the magnet assembly for converting received electrical signals into vibration signals of the glass diaphragm and making the flat panel display emitting sound.

Abstract: A passive sounding device integrated into a flat panel display includes a glass diaphragm having a first surface for forming a light-emitting array of the flat-panel display thereon, a suspension edge, and a frame, wherein the glass diaphragm is tightly sealed with the frame through the suspension edge to form an airtight space in the frame, and the glass diaphragm vibrates and emits sound in response to the pressure of the sound waves generated by an active sounding device.

Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first physical unit among a plurality of physical units based on a first electrical configuration to obtain first soft information; reading the first physical unit based on a second electrical configuration which is different from the first electrical configuration to obtain second soft information; classifying a plurality of memory cells in the first physical unit according to the first soft information and the second soft information; and decoding data read from the first physical unit according to a classification result of the memory cells.

Abstract: A sound wave transducer is provided. The sound wave transducer includes a first board, a spacer layer and a second board over the first board and the spacer layer. The first board includes a carrier, a first substrate layer and a first metal layer. The carrier has a first opening formed in a central region. The first substrate layer is disposed on the carrier and over the first opening. The first metal layer is disposed on the first substrate layer. The spacer layer is disposed on the first board and surrounds the central region. The second board includes a second substrate layer, a second metal layer disposed on the spacer layer, and a plurality of second openings penetrating through the second substrate layer and the second metal layer.

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: reading multiple first memory cells using multiple read voltage levels to obtain a first threshold voltage distribution of the first memory cells; obtaining shift information of the first threshold voltage distribution with respect to an original threshold voltage distribution of the first memory cells; obtaining first reliability information corresponding to the first threshold voltage distribution; recovering original reliability information corresponding to the original threshold voltage distribution according to a statistical characteristic of the first reliability information; adjusting the original reliability information according to the shift information to obtain second reliability information corresponding to the first threshold voltage distribution; and updating reliability information related to the first memory cells according to the second reliability information.

Abstract: A hybrid diaphragm structure is provided. The hybrid diaphragm structure includes a substrate, a first diaphragm disposed in a central region of the substrate, a first coil structure disposed over the first diaphragm, a first groove separating the first diaphragm and the first coil structure from the substrate, and a first bridge structure coupling the first diaphragm to the substrate. The first diaphragm and the substrate include a same material.

Abstract: A data protection method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes, and the plurality of disk array tags corresponding to one of the word lines connected to one of the memory planes are at least partially identical to the plurality of disk array tags corresponding to another one of the word lines connected to another one of the memory planes; receiving a write command and data corresponding to the write command from a host system; and sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.

Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first physical unit among a plurality of physical units based on a first electrical configuration to obtain first soft information; reading the first physical unit based on a second electrical configuration which is different from the first electrical configuration to obtain second soft information; classifying a plurality of memory cells in the first physical unit according to the first soft information and the second soft information; and decoding data read from the first physical unit according to a classification result of the memory cells.

Abstract: The present disclosure provides an electronic device, and a radio-frequency device and a signal transmission component thereof. The signal transmission component is operable in an operating frequency band and applied in a radio frequency device having a signal connector and a radio frequency circuit. The signal transmission component includes a signal transmission line and an electrostatic protection unit. The signal transmission line is disposed between the signal connector and the radio frequency circuit. The electrostatic protection unit is electrically connected to the signal transmission line, and includes a connecting end and a grounding end. An impedance of the electrostatic protection unit is greater than an impedance of the signal transmission line. An electrical length is defined between the connecting end and the grounding end, and the electrical length is less than ¼ of a wavelength corresponding to a lowest operating frequency within the operating frequency band.

Abstract: A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.

Abstract: A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.