Abstract: A readout system includes a sensing module to generate first and second voltage signals with a phase difference associated with an environmental parameter, and a readout module configured to calibrate the phase difference, and to convert the calibrated phase difference into an output code.

Abstract: A readout system includes a sensing module to generate first and second voltage signals with a phase difference associated with an environmental parameter, and a readout module configured to calibrate the phase difference, and to convert the calibrated phase difference into an output code.

Abstract: Multiple measurements are made with one memory sense operation having a first word line sensing voltage on a memory cell. The multiple measurements include a first measurement, of whether the memory cell stores either: (a) data corresponding to a first set of one or more threshold voltage ranges below the first word line sensing voltage of the one memory sense operation, or (b) data corresponding to a second set of one or more threshold voltage ranges above the first word line sensing voltage of the one memory sense operation. The multiple measurements include a second measurement, of error correction data of the memory cell indicating relative position within a particular threshold voltage range of a stored threshold voltage in the memory cell.

Abstract: A counting engine for a Bayesian sequential partition system in a D-dimensional data space is provided. The counting engine includes a filtering module and a counting module. The filtering module is used for comparing at least one under-test data point with D boundary information corresponding to a sub-region, and consequently generating D flag sets. The counting module is connected with the filtering module. The counting module determines whether the at least one under-test data point lies in the sub-region, and consequently generates a result signal. A counting value corresponding to the sub-region is selectively accumulated by the counting module according to the result signal.

Abstract: A solid state storage device and sensing voltage setting method thereof are provided, and the method includes following steps. A predetermined read voltage of the memory cells is adjusted to obtain a plurality of detection read voltages. The predetermined read voltage and the detection read voltages are respectively applied to a plurality of memory cells in order to read a plurality of verification bit data. A plurality of statistical parametric values between the predetermined read voltage and the detection read voltages adjacent to each other is calculated and recorded according to the verification bit data corresponding to the predetermined read voltage and the detection read voltages. An optimized read voltage is obtained according to the statistical parametric values.

Abstract: A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture.

Abstract: A data compensating method for a flash memory is provided. Firstly, a first threshold voltage distribution curve of the cells of the flash memory with a first storing state is acquired. Then, a second threshold voltage distribution curve of the cells of the flash memory with a second storing state is acquired. Then, a first occurrence probability of a first type ICI pattern of the first storing state is calculated according to a statistic voltage range and the first threshold voltage distribution curve. A second occurrence probability of the first type ICI pattern of the second storing state is acquired according to the statistic voltage range and the second threshold voltage distribution curve. During a read cycle, storing states of central cells corresponding to the first type ICI pattern are compensated according to the first occurrence probability and the second occurrence probability.

Abstract: A solid state storage device and sensing voltage setting method thereof are provided, and the method includes following steps. A predetermined read voltage of the memory cells is adjusted to obtain a plurality of detection read voltages. The predetermined read voltage and the detection read voltages are respectively applied to a plurality of memory cells in order to read a plurality of verification bit data. A plurality of statistical parametric values between the predetermined read voltage and the detection read voltages adjacent to each other is calculated and recorded according to the verification bit data corresponding to the predetermined read voltage and the detection read voltages. An optimized read voltage is obtained according to the statistical parametric values.

Abstract: A solid state storage device and controlling method thereof are provided, and the method includes following steps. Data is programmed into a flash memory module by using a first programming scheme. A data error parameter of the flash memory module is determined. If the data error parameter is greater than an error predefine value, the data is programmed into the flash memory module by using a second programming scheme. The first programming scheme and the second programming scheme are respectively mapping to a first threshold voltage frame and a second threshold voltage frame, and voltage interval of the second threshold voltage frame is broader than voltage interval of the first threshold voltage frame.

Abstract: A group classification method includes the following steps. Firstly, a voltage shift parameter table is established. The voltage shift parameter table includes a first positional parameter table corresponding to a first neighboring cell. Then, MN ICI patterns are determined according to N neighboring cells having a significant ICI effect. If the central cell has a first storing state, MN central cell threshold voltage shifts corresponding to the MN ICI patterns are determined according to the voltage shift parameter table, and the first storing state is divided into plural sub-regions. Afterwards, the central cells corresponding to a first number of ICI patterns are classified into a first group of the first storing state. The central cell threshold voltage shifts corresponding to the first number of ICI patterns lie in a first sub-region of the first storing state.

Abstract: In a cyclic code decoding method, a decoder analyzes a received codeword to identify unreliable symbols in the codeword, and sets candidate syndrome patterns accordingly. Then, a syndrome calculator calculates evaluated syndrome values associated with one of the candidate syndrome patterns, and an error location polynomial (ELP) generator generates an ELP according to the syndrome values. An error correction device corrects the errors in the codeword according to the ELP when a degree of the ELP is not more than a threshold value, and the syndrome calculator adjusts the syndrome values and the ELP generator generates another ELP according to the adjusted syndrome values when otherwise.

Abstract: A method for estimating a distribution curve of a first storing state of a solid state storage device includes the following steps. Firstly, plural threshold voltage intervals are provided. Numbers of cells within respective threshold voltage intervals are calculated. A location parameter interval is determined according to the numbers of cells within the threshold voltage intervals. The percentages of the cells within respective threshold voltage intervals are determined, and thus a distribution curve table is established. Then, m candidate location parameters within the location parameter interval are determined, and n candidate scale parameters are set. According to the m candidate location parameters and the n candidate scale parameters, m×n candidate Gaussian distribution curves are determined. A first Gaussian distribution curve selected from the m×n candidate Gaussian distribution curves is defined as the distribution curve.

Abstract: A group classification method includes the following steps. Firstly, a voltage shift parameter table is established. The voltage shift parameter table includes a first positional parameter table corresponding to a first neighboring cell. Then, MN ICI patterns are determined according to N neighboring cells having a significant ICI effect. If the central cell has a first storing state, MN central cell threshold voltage shifts corresponding to the MN ICI patterns are determined according to the voltage shift parameter table, and the first storing state is divided into plural sub-regions. Afterwards, the central cells corresponding to a first number of ICI patterns are classified into a first group of the first storing state. The central cell threshold voltage shifts corresponding to the first number of ICI patterns lie in a first sub-region of the first storing state.

Abstract: A joint encoding/decoding method for a solid state drive is provided. Firstly, a data-writing process is implemented for encoding a user data by a hard codec and a soft codec respectively, thereby generating a first number of parity bits and a second number of parity bits. Then, the user data, the first number of parity bits and the second number of parity bits are written into a flash memory module. Then, a data-reading process is implemented for decoding the user data by the hard codec according to the first number of parity bits. If the user data is successfully decoded, the user data is outputted. If the user data is unsuccessfully decoded, a step of decoding the user data by the soft codec according to the second number of parity bits is performed.

Abstract: A method for determining a storing state of a flash memory is provided. The method includes the following steps. Firstly, plural first specific cell patterns are programmed into the flash memory. Then, plural second specific cell patterns are programmed into the flash memory. Then, a slicing voltage is adjusted to allow a distinguishable error percentage to be lower than a predetermined value. Afterwards, a first storing state and a second storing state of other cells of the flash memory are distinguished from each other according to the adjusted slicing voltage.

Abstract: A data compensating method for a flash memory is provided. Firstly, a first threshold voltage distribution curve of the cells of the flash memory with a first storing state is acquired. Then, a second threshold voltage distribution curve of the cells of the flash memory with a second storing state is acquired. Then, a first occurrence probability of a first type ICI pattern of the first storing state is calculated according to a statistic voltage range and the first threshold voltage distribution curve. A second occurrence probability of the first type ICI pattern of the second storing state is acquired according to the statistic voltage range and the second threshold voltage distribution curve. During a read cycle, storing states of central cells corresponding to the first type ICI pattern are compensated according to the first occurrence probability and the second occurrence probability.

Abstract: A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture.

Abstract: Multiple measurements are made with one memory sense operation having a first word line sensing voltage on a memory cell. The multiple measurements include a first measurement, of whether the memory cell stores either: (a) data corresponding to a first set of one or more threshold voltage ranges below the first word line sensing voltage of the one memory sense operation, or (b) data corresponding to a second set of one or more threshold voltage ranges above the first word line sensing voltage of the one memory sense operation. The multiple measurements include a second measurement, of error correction data of the memory cell indicating relative position within a particular threshold voltage range of a stored threshold voltage in the memory cell.

Abstract: An apparatus of processing polynomials includes at least one reconfigurable module and an encoder controller. The reconfigurable module includes a plurality of linear feedback shift registers. The encoder controller can control the reconfigurable module to factor a generator polynomial into a factorial polynomial. In the reconfigurable module, the linear feedback shift registers can register a plurality of factors of the factorial polynomial respectively.

Abstract: A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics.