Patents by Inventor Hsien A. Chen

Hsien A. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096806
    Abstract: A method for manufacturing a semiconductor structure is provided. A substrate including a fin structure is received, provided or formed. A sacrificial gate layer is formed over the fin structure and a source/drain structure is formed adjacent to the sacrificial gate layer, wherein the sacrificial gate layer is surrounded by a dielectric structure. The sacrificial gate layer is removed, wherein a recess is defined by the dielectric structure. A work function layer is formed in the recess, wherein the work function layer includes an overhang portion at an opening of the recess. A thickness of the work function layer is reduced. A glue layer is formed over the work function layer. A semiconductor structure thereof is also provided.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 21, 2024
    Inventors: CHAO-HSUAN CHEN, WEI CHEN HUNG, LI-WEI YIN, YU-HSIEN LIN, YIH-ANN LIN, RYAN CHIA-JEN CHEN
  • Publication number: 20240098932
    Abstract: A foldable electronic device, including a first body, a second body, an air valve movably disposed in the first body, at least one triggering member, and a hinge connecting the first body and the second body, is provided. The first body has multiple openings respectively located at two opposite surfaces. The triggering member is movably disposed in the first body and has a part exposed outside the first body. The air valve and the triggering member are mutually on moving paths of each other. The first body and the second body are rotated to be folded or unfolded relative to each other by the hinge. A part of the triggering member is suitable for bearing a force such that the triggering member drives the air valve, so that the air valve opens or closes the openings.
    Type: Application
    Filed: July 19, 2023
    Publication date: March 21, 2024
    Applicant: Acer Incorporated
    Inventors: Hui-Ping Sun, Jui-Yi Yu, Chun-Hung Wen, Yen-Chou Chueh, Yu-Ming Lin, Chun-Hsien Chen
  • Publication number: 20240093416
    Abstract: A sewing machine includes a main body and a quick release needle plate module. The main body includes a base seat having an inner frame, and an outer case that is mounted to the inner frame and that defines an accommodating compartment. The quick release needle plate module includes a catch member, and a needle plate that covers the accommodating compartment, that is detachably pivoted to a rear section of the inner frame, and that engages the catch member. The quick release needle plate module further includes a press member inserted through the outer case and the inner frame, and operable to push the catch member to disengage the catch member. The needle plate has a plate body that covers the accommodating compartment, and a resilient member mounted between the inner frame and the plate body for driving pivot action of the plate body away from the inner frame.
    Type: Application
    Filed: January 20, 2023
    Publication date: March 21, 2024
    Applicant: ZENG HSING INDUSTRIAL CO., LTD.
    Inventors: Kun-Lung HSU, Ming-Ta LEE, Wei-Chen CHEN, Po-Hsien TSENG
  • Publication number: 20240094282
    Abstract: A circuit test structure includes a chip including a conductive line which traces a perimeter of the chip. The circuit test structure further includes an interposer electrically connected to the chip, wherein the conductive line is over both the chip and the interposer. The circuit test structure further includes a test structure connected to the conductive line. The circuit test structure further includes a testing site, wherein the test structure is configured to electrically connect the testing site to the conductive line.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: Ching-Fang CHEN, Hsiang-Tai LU, Chih-Hsien LIN
  • Publication number: 20240092662
    Abstract: A method for removing a heavy metal from water includes subjecting a microbial solution containing a liquid culture of a urease-producing bacterial strain and a reaction solution containing a manganese compound and urea to a microbial-induced precipitation reaction, so as to obtain biomineralized manganese carbonate (MnCO3) particles, admixing the biomineralized MnCO3 particles with water containing a heavy metal, so that the biomineralized MnCO3 particles adsorb the heavy metal in the water to form a precipitate, and removing the precipitate from the water.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 21, 2024
    Inventors: Chien-Yen CHEN, Yi-Hsun HUANG, Pin-Yun LIN, Anggraeni Kumala DEWI, Koyeli DAS, Uttara SUKUL, Tsung-Hsien CHEN, Raju Kumar SHARMA, Cheng-Kang LU, Chung-Ming LU
  • Patent number: 11934223
    Abstract: A foldable electronic device, including a first body having a first shaft member, at least one second body having a second shaft member, and a latching member, is provided. The first shaft member and the second shaft member are coaxially pivoted together. The first shaft member has a recess. The second shaft member has a locking hole. The latching member is movably disposed in the recess and the locking hole, so that when the latching member leaves the locking hole, the first body and the second body are relatively pivoted through the first shaft member and the second shaft member, or when the latching member moves into the locking hole, the latching member interferes with the first shaft member and the second shaft member to block the first body and the second body from relatively pivoting.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: March 19, 2024
    Assignee: Acer Incorporated
    Inventors: Hui-Ping Sun, Chun-Hung Wen, Yen-Chou Chueh, Chun-Hsien Chen
  • Patent number: 11936927
    Abstract: A multimedia signal transmission control system is provided, which includes a transmitter control circuit and a receiver control circuit coupled with each other. The transmitter control circuit packs a control signal and at least one of multimedia signals into first hybrid data packets in an active video period of a video frame, and packs the control signal and another at least one of the multimedia signals into second hybrid data packets in a vertical front porch and a vertical back porch of the video frame. The receiver control circuit receives the first hybrid data packets in the active video period, and receives the second hybrid data packets in the vertical front porch and the vertical back porch. The receiver control circuit unpacks the first hybrid data packets and the second hybrid data packets to provide the control signal and the multimedia signals to a display module.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: March 19, 2024
    Assignee: Realtek Semiconductor Corporation
    Inventors: Yun-Hung Lin, Po-Hsien Wu, Li-Yu Chen
  • Patent number: 11935728
    Abstract: In order to reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Cheng Wu, Sheng-Ying Wu, Ming-Hsien Lin, Chun Fu Chen
  • Patent number: 11934107
    Abstract: Embodiments described herein relate to methods of forming layers using maskless based lithography. In these embodiments, the methods implement ladders of dose change such that a geometric shape can be divided into overlaying sections. The overlaying sections can include a different dose of each section such that taper control can be achieved. The taper can be achieved by manipulating the geometry “mask data” into overlaying sections that are exposed by various doses controlled by pixel blending (PB) exposure techniques. To perform the methods described herein, a maskless lithography tool is used. The maskless lithography tool includes a controller that performs software based “mask data” manipulation.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: March 19, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shih-Hsien Lee, Tingwei Chiu, Frederick Lie, Jang Fung Chen
  • Publication number: 20240088122
    Abstract: A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Jie Chen, Hsien-Wei Chen, Ming-Fa Chen, Chen-Hua Yu
  • Publication number: 20240088124
    Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
  • Publication number: 20240088027
    Abstract: An integrated circuit includes an inductor that includes a first set of conductors in at least a first metal layer, and a guard ring enclosing the inductor. The guard ring includes a first conductor extending in a first direction, a second conductor extending in a second direction, and a first set of staggered conductors coupled to a first end of the first conductor and a first end of the second conductor. The first set of staggered conductors includes a second set of conductors in a second metal layer, a third set of conductors in a third metal layer and a first set of vias coupling the second set of conductors with the third set of conductors. The third metal layer is above the second metal layer. All metal lines in the second metal layer that are part of the guard ring extend in the first direction.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Chiao-Han LEE, Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
  • Publication number: 20240088028
    Abstract: A semiconductor package includes a die and a plurality of conductive patterns. The die includes a device. The conductive patterns are disposed over the device, wherein the conductive patterns are electrically connected to one another to form a first coil and a second coil surrounding the first coil.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20240079324
    Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.
    Type: Application
    Filed: November 7, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie CHEN, Ying-Ju CHEN, Chen-Hua YU, Der-Chyang YEH, Hsien-Wei CHEN
  • Publication number: 20240077805
    Abstract: Embodiments described herein relate to methods of forming layers using maskless based lithography. In these embodiments, the methods implement ladders of dose change such that a geometric shape can be divided into overlaying sections. The overlaying sections can include a different dose of each section such that taper control can be achieved. The taper can be achieved by manipulating the geometry “mask data” into overlaying sections that are exposed by various doses controlled by pixel blending (PB) exposure techniques. To perform the methods described herein, a maskless lithography tool is used. The maskless lithography tool includes a controller that performs software based “mask data” manipulation.
    Type: Application
    Filed: October 9, 2019
    Publication date: March 7, 2024
    Inventors: Shih-Hsien LEE, Tingwei CHIU, Frederick LIE, Jang Fung CHEN
  • Patent number: 11923252
    Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chi-On Chui, Chih-Chieh Yeh, Cheng-Hsien Wu, Chih-Sheng Chang, Tzu-Chiang Chen, I-Sheng Chen
  • Publication number: 20240071799
    Abstract: A system for a semiconductor fabrication facility comprises a transporting tool configured to move a carrier, a first manufacturing tool configured to accept the carrier facing in a first direction, a second manufacturing tool configured to accept the carrier facing in the second direction, and an orientation tool. The carrier is moved to the orientation tool by the transporting tool prior to being moved to the first manufacturing tool or the second manufacturing tool by the transporting tool. The orientation tool rotates the carrier so that the carrier is accepted by the first manufacturing tool or the second manufacturing tool. The transporting tool, the first manufacturing tool, the second manufacturing tool and the orientation tool are physically separated from each other.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventors: CHUAN WEI LIN, FU-HSIEN LI, YONG-JYU LIN, RONG-SHEN CHEN, CHI-FENG TUNG, HSIANG YIN SHEN
  • Publication number: 20240072021
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Patent number: D1018527
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 19, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Han-Tsai Liu, Jyh-Chyang Tzou, Cheng-Shiue Jan, Yao-Hsien Yang, Pai-Feng Chen, I-Hao Chen
  • Patent number: D1018774
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: March 19, 2024
    Assignee: HOMEWAY TECHNOLOGY CO., LTD.
    Inventors: Ming-Kun Chen, Chin-Hsing Hsieh, Tsung-Hsien Hsieh