Patents by Inventor Hsien-Hsin Sean LEE

Hsien-Hsin Sean LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12093176
    Abstract: A memory system includes multiple groups of primary memory cells residing in a first die or a stack of first dies, multiple groups of cache memory cells residing in a second die, an interposer, and control circuits residing in a third die. Each group of the cache memory cells is associated with a corresponding group of the primary memory cells. The first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps. A bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps. The control circuits are associated with the primary memory cells and the cache memory cells. The third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Hsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
  • Publication number: 20240256751
    Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.
    Type: Application
    Filed: July 19, 2023
    Publication date: August 1, 2024
    Inventors: Nien-Yu TSAI, Chin-Chang HSU, Wen-Ju YANG, Hsien-Hsin Sean LEE
  • Publication number: 20230385511
    Abstract: A system for manufacturing an integrated circuit includes a non-transitory computer readable medium configured to store executable instructions, and a processor coupled to the non-transitory computer readable medium. The processor is configured to execute the executable instructions for placing a set of gate layout patterns on a first layout level, and generating a cut feature layout pattern extending in the first direction. The set of gate layout patterns correspond to fabricating a set of gate structures of the integrated circuit. The cut feature layout pattern is on the first layout level, and overlap each of the layout patterns of the set of gate layout patterns at a same position in the second direction. The cut feature layout pattern identifies a location of a removed portion of a gate structure of the set of gate structures.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Yu-Jung CHANG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Wen-Ju YANG
  • Publication number: 20230333981
    Abstract: A memory system includes multiple groups of primary memory cells residing in a first die or a stack of first dies, multiple groups of cache memory cells residing in a second die, an interposer, and control circuits residing in a third die. Each group of the cache memory cells is associated with a corresponding group of the primary memory cells. The first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps. A bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps. The control circuits are associated with the primary memory cells and the cache memory cells. The third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 19, 2023
    Inventors: Hsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
  • Patent number: 11775724
    Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jung Chang, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
  • Publication number: 20230260268
    Abstract: A console and headset system locally trains machine learning models to perform customized online learning tasks. To customize the online learning models for specific users of the system without using outside resources, the system trains the models to compare a target frame to stored calibration frames, rather than directly inferring information about a target frame. During deployment, an embedding is generated for the target frame. A sample embedding that is closest to the target embedding is selected from a group of embeddings of calibration frames. The information about the selected embedding and target embedding and ground truths for the calibration frame are provided as inputs to one of the trained models. The model predicts a difference between the target frame and the calibration frame, which can be used to determine information about the target frame.
    Type: Application
    Filed: March 29, 2022
    Publication date: August 17, 2023
    Inventors: Syed Shakib Sarwar, Manan Suri, Vivek Kamalkant Parmar, Ziyun Li, Barbara De Salvo, Hsien-Hsin Sean Lee
  • Patent number: 11714946
    Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Yang, Hsien-Hsin Sean Lee
  • Patent number: 11687454
    Abstract: A memory circuit includes a stack of first dies including multiple sets of memory cells of a first type, a second die including multiple sets of memory cells of a second type, a third die, and an interposer carrying the first, second, and third dies. The second die includes a first set of input/output (I/O) terminals on a top surface of the second die and a second set of I/O terminals on a bottom surface of the second die. The stack of first dies is coupled to the second die through the first set of I/O terminals. The interposer is coupled to the second die through the second set of I/O terminals. The third die is positioned aside the second die and in communication with the second die through the interposer.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
  • Patent number: 11681850
    Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Preet Yang, Hsien-Hsin Sean Lee
  • Patent number: 11442866
    Abstract: A device (e.g., an application-specific integrated circuit chip) includes a memory module processing unit and an interface. The memory module processing unit is configured to receive an instruction to obtain values stored in one or more memory components and process the obtained values to return a processed result. The memory module processing unit is also configured to store the obtained values in a cache based on one or more criteria. The memory module processing unit is configured to be included on a computer memory module configured to be installed in a computer system. The interface is configured to communicate with the one or more memory components included on the computer memory module.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: September 13, 2022
    Assignee: Meta Platforms, Inc.
    Inventors: Liu Ke, Xuan Zhang, Udit Gupta, Carole-Jean Wu, Mark David Hempstead, Brandon Reagen, Hsien-Hsin Sean Lee
  • Publication number: 20220129382
    Abstract: A memory circuit includes a stack of first dies including multiple sets of memory cells of a first type, a second die including multiple sets of memory cells of a second type, a third die, and an interposer carrying the first, second, and third dies. The second die includes a first set of input/output (I/O) terminals on a top surface of the second die and a second set of I/O terminals on a bottom surface of the second die. The stack of first dies is coupled to the second die through the first set of I/O terminals. The interposer is coupled to the second die through the second set of I/O terminals. The third die is positioned aside the second die and in communication with the second die through the interposer.
    Type: Application
    Filed: January 4, 2022
    Publication date: April 28, 2022
    Inventors: Hsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
  • Publication number: 20220027545
    Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Inventors: Yu-Jung CHANG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Wen-Ju YANG
  • Patent number: 11216376
    Abstract: A memory circuit includes a first memory circuit formed of a first die or a set of stacked dies. The memory circuit further includes a second memory circuit formed of a second die, the second memory circuit comprising one or more sets of memory cells of a second type and each set of the memory cells of the second type comprising multiple cache sections. The first die or the set of stacked dies are stacked over the second die, wherein the second die further includes a first plurality of I/O terminals and a second plurality of I/O terminals, the first plurality of I/O terminals being electrically coupled to the first memory circuit, and the second plurality of I/O terminals being electrically isolated from the first memory circuit.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
  • Publication number: 20210365623
    Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.
    Type: Application
    Filed: August 5, 2021
    Publication date: November 25, 2021
    Inventors: Nien-Yu TSAI, Chin-Chang HSU, Wen-Ju YANG, Hsien-Hsin Sean LEE
  • Patent number: 11138361
    Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jung Chang, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
  • Publication number: 20210279398
    Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nien-Yu TSAI, Chin-Chang HSU, Wen-Ju Preet YANG, Hsien-Hsin Sean Lee
  • Patent number: 11106852
    Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
  • Patent number: 11062075
    Abstract: A method of manufacturing an integrated circuit includes generating a layout design of the integrated circuit, manufacturing the integrated circuit based on the layout design, and removing a portion of a gate structure of a set of gate structures thereby forming a first and a second gate structure. Generating the layout design includes placing a set of gate layout patterns and a cut feature layout pattern on the first layout level. The cut feature layout pattern extends in a first direction, overlaps the set of gate layout patterns and identifies a location of the portion of the gate structure of the set of gate structures. The set of gate layout patterns correspond to fabricating a set of gate structures. The set of gate layout patterns extending in a second direction and overlapping a set of gridlines that extend in the second direction.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jung Chang, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
  • Publication number: 20210191871
    Abstract: A device (e.g., an application-specific integrated circuit chip) includes a memory module processing unit and an interface. The memory module processing unit is configured to receive an instruction to obtain values stored in one or more memory components and process the obtained values to return a processed result. The memory module processing unit is also configured to store the obtained values in a cache based on one or more criteria. The memory module processing unit is configured to be included on a computer memory module configured to be installed in a computer system. The interface is configured to communicate with the one or more memory components included on the computer memory module.
    Type: Application
    Filed: February 6, 2020
    Publication date: June 24, 2021
    Inventors: Liu Ke, Xuan Zhang, Udit Gupta, Carole-Jean Wu, Mark David Hempstead, Brandon Reagen, Hsien-Hsin Sean Lee
  • Patent number: 11017148
    Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Preet Yang, Hsien-Hsin Sean Lee