Patents by Inventor Hsien-Hsin Sean LEE

Hsien-Hsin Sean LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9846761
    Abstract: A layout of an integrated circuit design is provided and a plurality of multiple patterning decompositions is determined from the layout. Each decomposition of the plurality of multiple patterning decompositions includes patterns separated into masks. One or more files are generated that include sensitivities of pattern capacitances to changes in spacing between patterns due to mask shifts. Using the sensitivities and changes in spacing, respective worst-case performance values are determined for each decomposition. A mask set is selected based on the worst-case performance values.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: December 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Chou, Te-Yu Liu, Ke-Ying Su, Hsien-Hsin Sean Lee
  • Publication number: 20170316142
    Abstract: A method, of generating a modified layout based on an original layout, includes: determining a first set of width bias values of an i-th set of layout patterns which compensate for subtractive process effects, the original layout having N sets of layout patterns corresponding to N masks; determining a second set of width bias values of the i-th set of layout patterns of the original layout which compensate for additive process effects; generating the modified layout based on the first and second sets of width bias values of the i-th set of layout patterns, the order index i of the i-th mask corresponding to an order of the i-th mask being applied during a fabrication process; and fabricating, based on the modified layout, at least one of a semiconductor mask or at least one component in a layer of an inchoate semiconductor integrated circuit.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Chia-Ming HO, Ke-Ying SU, Hsien-Hsin Sean LEE
  • Patent number: 9710588
    Abstract: A method of includes determining a first set of width bias values of an i-th set of layout patterns of an original layout according a first type width variation. The original layout has N sets of layout patterns corresponding to N masks, where the i-th set of layout patterns has an i-th mask assignment corresponding to an i-th mask of the N masks. The order index i is an integer from 1 to N, and N is an integer and greater than 1. A second set of width bias values of the i-th set of layout patterns of the original layout is determined according to a second type width variation. The modified layout is generated based on the first and second sets of width bias values of the i-th set of layout patterns.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming Ho, Ke-Ying Su, Hsien-Hsin Sean Lee
  • Publication number: 20170199957
    Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph. The method further includes partitioning, using a specific purpose processing device, the decomposed conflict graph if the decomposed conflict graph is not a simplified graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device if the decomposed conflict graph is a simplified graph. The method further includes flagging violations if the decomposed conflict graph is not colorable.
    Type: Application
    Filed: January 7, 2016
    Publication date: July 13, 2017
    Inventors: Chung-Yun CHENG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Jian-Yi LI, Li-Sheng KE, Wen-Ju YANG
  • Publication number: 20170161424
    Abstract: A method for designing a semiconductor device includes establishing boundary conditions for a layout of each cell of a plurality of cells, wherein each cell has a plurality of features, and boundary conditions are established based on a proximity of each feature to a cell boundary of a corresponding cell. The method includes determining whether the layout of each cell is colorable based on a number of masks used to manufacture a layer of the semiconductor device, a minimum spacing requirement for the plurality of features, and the established boundary conditions. The method includes forming a layout of the layer of the semiconductor device by abutting a first cell of the plurality of cells with a second cell of the plurality of cells. The method includes reporting the layout of the layer of the semiconductor device as colorable without analyzing the layout of the layer of the semiconductor device.
    Type: Application
    Filed: December 2, 2015
    Publication date: June 8, 2017
    Inventors: Nien-Yu TSAI, Chin-Chang HSU, Hsien-Hsin Sean LEE, Wen-Ju YANG
  • Patent number: 9666490
    Abstract: Methods for fabricating multiple inverter structures in a multi-layer semiconductor structure are provided. A first device layer is formed on a substrate. The first device layer comprises one or more first inverter structures including a first input terminal and a first output terminal. A second device layer is formed on the first device layer. The second device layer comprises one or more second inverter structures including a second input terminal and a second output terminal. One or more inter-layer connection structures are formed. The one or more inter-layer connection structures are disposed to electrically connect the first input terminal to the second output terminal and electrically connect the first output terminal to the second input terminal.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Fan Lin, Yi-Tang Lin, Cheng-Hung Yeh, Hsien-Hsin Sean Lee, Chou-Kun Lin
  • Patent number: 9582630
    Abstract: One or more systems and methods for a cell based hybrid resistance and capacitance (RC) extraction are provided. The method includes generating a layout for a semiconductor arrangement, performing a three-dimensional (3D) RC extraction on a target unit cell to obtain a 3D RC result including a coupling capacitance between unit cells, generating a 3D RC netlist based upon the 3D RC result, performing a 2.5 dimensional (2.5D) RC extraction on a peripheral cell to obtain a 2.5D RC netlist, and combining the 3D RC netlist with the 2.5D RC netlist to create a hybrid RC netlist for the layout. In some embodiments, the hybrid RC netlist is generated by stitching the coupling capacitance for at least one of the target unit cell, a repeating unit cell, or the peripheral cell together. In some embodiments, the 3D RC result for the target unit cell is stitched to the repeating unit cell.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ze-Ming Wu, Shih Hsin Chen, Chien-Chih Kuo, Kai-Ming Liu, Hsien-Hsin Sean Lee
  • Publication number: 20170004252
    Abstract: A layout of an integrated circuit design is provided and a plurality of multiple patterning decompositions is determined from the layout. Each decomposition of the plurality of multiple patterning decompositions includes patterns separated into masks. One or more files are generated that include sensitivities of pattern capacitances to changes in spacing between patterns due to mask shifts. Using the sensitivities and changes in spacing, respective worst-case performance values are determined for each decomposition. A mask set is selected based on the worst-case performance values.
    Type: Application
    Filed: September 15, 2016
    Publication date: January 5, 2017
    Inventors: Chih-Cheng CHOU, Te-Yu LIU, Ke-Ying SU, Hsien-Hsin Sean LEE
  • Publication number: 20160364331
    Abstract: A method of operating a memory circuit is disclosed. The memory circuit comprises a primary memory and a cache memory. The primary memory has P access channels of Q bits of channel bandwidth, and the cache memory has P subsets of Q*N memory cells, wherein P and Q are integers greater than 1, and N is a positive integer. The method includes determining, in response to a command for reading first and second data accessible through first and second access channels respectively, if a valid duplication of the first and second data is stored in the cache memory. If yes, the method further includes storing a duplication of Q*n bits of consecutively addressed data from each of the first and second access channels to the cache memory, n being an integer from 1 to N. Otherwise, the method further includes outputting the first and second data from the cache memory.
    Type: Application
    Filed: August 26, 2016
    Publication date: December 15, 2016
    Inventors: Hsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
  • Patent number: 9471738
    Abstract: A method comprises processing a layout of an integrated circuit to determine one or more attributes of one or more components of the integrated circuit. The method also comprises extracting one or more process parameters from a process file associated with manufacturing the integrated circuit. The one or more process parameters are extracted from the process file based on a computation of one or more logic functions included in the process file. The computation is based on the one or more attributes. The method further comprises calculating a capacitance value between at least two components of the integrated circuit based on the one or more process parameters and a capacitance determination rule included in the process file. At least one of the one or more process parameters, the one or more logic functions, or the capacitance determination rule is editable based on a user input.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: October 18, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Chou, Tsung-Han Wu, Ke-ying Su, Hsien-Hsin Sean Lee, Chung-Hsing Wang
  • Publication number: 20160284603
    Abstract: Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.
    Type: Application
    Filed: June 6, 2016
    Publication date: September 29, 2016
    Inventors: I-Fan Lin, YI-TANG LIN, CHENG-HUNG YEH, HSIEN-HSIN SEAN LEE, CHOU-KUN LIN
  • Patent number: 9448467
    Abstract: A system and method comprising providing a layout of an integrated circuit design, generating, by a processor, a plurality of multiple patterning decompositions from the layout, determining a maximum mask shift between the first mask and the second mask and simulating a worst-case performance value for each of the plurality of multiple patterning decompositions using one or more mask shifts within a range defined by the maximum mask shift. Further, each of the plurality of multiple patterning decompositions comprise patterns separated to a first mask and a second mask of a multiple patterning mask set.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Chou, Te-Yu Liu, Ke-Ying Su, Hsien-Hsin Sean Lee
  • Patent number: 9431064
    Abstract: A cache memory die includes a substrate, a predetermined number of sets of memory cells on the substrate, a first set of input/output terminals on a first surface of the cache memory die, and a second set of input/output terminals on a second surface of the cache memory die. The first set of input/output terminals are connected to a primary memory circuit outside the cache memory die. A portion of the second set of input/output terminals are compatible with the first set of input/output terminals.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
  • Publication number: 20160232270
    Abstract: A method comprises processing a layout of an integrated circuit to determine one or more attributes of one or more components of the integrated circuit. The method also comprises extracting one or more process parameters from a process file associated with manufacturing the integrated circuit. The one or more process parameters are extracted from the process file based on a computation of one or more logic functions included in the process file. The computation is based on the one or more attributes. The method further comprises calculating a capacitance value between at least two components of the integrated circuit based on the one or more process parameters and a capacitance determination rule included in the process file. At least one of the one or more process parameters, the one or more logic functions, or the capacitance determination rule is editable based on a user input.
    Type: Application
    Filed: February 5, 2015
    Publication date: August 11, 2016
    Inventors: Chih-Cheng CHOU, Tsung-Han WU, Ke-Ying SU, Hsien-Hsin Sean LEE, Chung-Hsing WANG
  • Patent number: 9373623
    Abstract: Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Fan Lin, Yi-Tang Lin, Cheng-Hung Yeh, Hsien-Hsin Sean Lee, Chou-Kun Lin
  • Publication number: 20160147928
    Abstract: A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 26, 2016
    Inventors: Chia-Ming HO, Adari Rama Bhadra RAO, Meng-Kai HSU, Kuang-Hung CHANG, Ke-Ying SU, Wen-Hao CHEN, Hsien-Hsin Sean LEE
  • Patent number: 9330215
    Abstract: A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic (“LVS”) check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Hsien Tsai, Chi-Ting Huang, Cheng-Hung Yeh, Hsien-Hsin Sean Lee
  • Publication number: 20160063165
    Abstract: One or more systems and methods for a cell based hybrid resistance and capacitance (RC) extraction are provided. The method includes generating a layout for a semiconductor arrangement, performing a 3D RC extraction on a target unit cell to obtain a 3D RC result including a coupling capacitance between unit cells, generating a 3D RC netlist based upon the 3D RC result, performing a 2.5D RC extraction on a peripheral cell to obtain a 2.5D RC netlist, and combining the 3D RC netlist with the 2.5D RC netlist to create a hybrid RC netlist for the layout. In some embodiments, the hybrid RC netlist is generated by stitching the coupling capacitance for at least one of the target unit cell, a repeating unit cell, or the peripheral cell together. In some embodiments, the 3D RC result for the target unit cell is stitched to the repeating unit cell.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 3, 2016
    Inventors: Ze-Ming Wu, Shih Hsin Chen, Chien-Chih Kuo, Kai-Ming Liu, Hsien-Hsin Sean Lee
  • Publication number: 20160042108
    Abstract: A method of includes determining a first set of width bias values of an i-th set of layout patterns of an original layout according a first type width variation. The original layout has N sets of layout patterns corresponding to N masks, where the i-th set of layout patterns has an i-th mask assignment corresponding to an i-th mask of the N masks. The order index i is an integer from 1 to N, and N is an integer and greater than 1. A second set of width bias values of the i-th set of layout patterns of the original layout is determined according to a second type width variation. The modified layout is generated based on the first and second sets of width bias values of the i-th set of layout patterns.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 11, 2016
    Inventors: Chia-Ming HO, Ke-Ying SU, Hsien-Hsin Sean LEE
  • Publication number: 20150269303
    Abstract: A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic (“LVS”) check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 24, 2015
    Applicant: Taiwan Semiconcuctor Manufacturing Co., Ltd.
    Inventors: Yao-Hsien TSAI, Chi-Ting HUANG, Cheng-Hung YEH, Hsien-Hsin Sean LEE