Patents by Inventor Hsien-Hsin Sean LEE
Hsien-Hsin Sean LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10713407Abstract: A standard cell for a semiconductor device includes a plurality of features for performing the functionality of the standard cell. The standard cell further includes a first sensitivity region adjacent to a first edge of the standard cell. The standard cell further includes anchor nodes linked to corresponding features of the plurality of features, wherein a number of anchor nodes linked to each feature of the corresponding features is based on a position of an end of each feature of the corresponding features relative to the first sensitivity region.Type: GrantFiled: December 24, 2018Date of Patent: July 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
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Publication number: 20200167519Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.Type: ApplicationFiled: September 30, 2019Publication date: May 28, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nien-Yu TSAI, Chin-Chang HSU, Wen-Ju Preet YANG, Hsien-Hsin Sean Lee
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Publication number: 20200117848Abstract: A method including decomposing a conflict graph based on a number of masked to be used to manufacture a semiconductor device. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes indicating that the conflict graph is colorable in response to a determination that the decomposed conflict graph is colorable.Type: ApplicationFiled: December 11, 2019Publication date: April 16, 2020Inventors: Chung-Yun CHENG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Jian-Yi LI, Li-Sheng KE, Wen-Ju YANG
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Publication number: 20200097629Abstract: A method of manufacturing an integrated circuit includes generating a layout design of the integrated circuit, manufacturing the integrated circuit based on the layout design, and removing a portion of a gate structure of a set of gate structures thereby forming a first and a second gate structure. Generating the layout design includes placing a set of gate layout patterns and a cut feature layout pattern on the first layout level. The cut feature layout pattern extends in a first direction, overlaps the set of gate layout patterns and identifies a location of the portion of the gate structure of the set of gate structures. The set of gate layout patterns correspond to fabricating a set of gate structures. The set of gate layout patterns extending in a second direction and overlapping a set of gridlines that extend in the second direction.Type: ApplicationFiled: November 25, 2019Publication date: March 26, 2020Inventors: Yu-Jung CHANG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Wen-Ju YANG
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Publication number: 20200097630Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.Type: ApplicationFiled: November 25, 2019Publication date: March 26, 2020Inventors: Yu-Jung CHANG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Wen-Ju YANG
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Publication number: 20200026648Abstract: A memory circuit includes a first memory circuit formed of a first die or a set of stacked dies. The memory circuit further includes a second memory circuit formed of a second die, the second memory circuit comprising one or more sets of memory cells of a second type and each set of the memory cells of the second type comprising multiple cache sections. The first die or the set of stacked dies are stacked over the second die, wherein the second die further includes a first plurality of I/O terminals and a second plurality of I/O terminals, the first plurality of I/O terminals being electrically coupled to the first memory circuit, and the second plurality of I/O terminals being electrically isolated from the first memory circuit.Type: ApplicationFiled: September 30, 2019Publication date: January 23, 2020Inventors: Hsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
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Patent number: 10515185Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes flagging violations in response to a determination that the decomposed conflict graph is not colorable.Type: GrantFiled: February 11, 2019Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Yun Cheng, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Jian-Yi Li, Li-Sheng Ke, Wen-Ju Yang
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Patent number: 10509883Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.Type: GrantFiled: January 24, 2017Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsun-Yu Yang, Wei-Yi Hu, Jui-Feng Kuan, Hsien-Hsin Sean Lee, Po-Cheng Pan, Hung-Wen Huang, Hung-Ming Chen, Abhishek Patyal
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Patent number: 10489548Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.Type: GrantFiled: January 3, 2018Date of Patent: November 26, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jung Chang, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
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Patent number: 10430544Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.Type: GrantFiled: September 2, 2016Date of Patent: October 1, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Preet Yang, Hsien-Hsin Sean Lee
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Patent number: 10430334Abstract: A method of operating a memory circuit is disclosed. The memory circuit comprises a primary memory and a cache memory. The primary memory has P access channels of Q bits of channel bandwidth, and the cache memory has P subsets of Q*N memory cells, wherein P and Q are integers greater than 1, and N is a positive integer. The method includes determining, in response to a command for reading first and second data accessible through first and second access channels respectively, if a valid duplication of the first and second data is stored in the cache memory. If yes, the method further includes storing a duplication of Q*n bits of consecutively addressed data from each of the first and second access channels to the cache memory, n being an integer from 1 to N. Otherwise, the method further includes outputting the first and second data from the cache memory.Type: GrantFiled: August 26, 2016Date of Patent: October 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
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Publication number: 20190171789Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes flagging violations in response to a determination that the decomposed conflict graph is not colorable.Type: ApplicationFiled: February 11, 2019Publication date: June 6, 2019Inventors: Chung-Yun CHENG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Jian-Yi LI, Li-Sheng KE, Wen-Ju YANG
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Publication number: 20190130061Abstract: A standard cell for a semiconductor device includes a plurality of features for performing the functionality of the standard cell. The standard cell further includes a first sensitivity region adjacent to a first edge of the standard cell. The standard cell further includes anchor nodes linked to corresponding features of the plurality of features, wherein a number of anchor nodes linked to each feature of the corresponding features is based on a position of an end of each feature of the corresponding features relative to the first sensitivity region.Type: ApplicationFiled: December 24, 2018Publication date: May 2, 2019Inventors: Nien-Yu TSAI, Chin-Chang HSU, Hsien-Hsin Sean LEE, Wen-Ju YANG
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Patent number: 10204205Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph. The method further includes partitioning, using a specific purpose processing device, the decomposed conflict graph if the decomposed conflict graph is not a simplified graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device if the decomposed conflict graph is a simplified graph. The method further includes flagging violations if the decomposed conflict graph is not colorable.Type: GrantFiled: January 7, 2016Date of Patent: February 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Yun Cheng, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Jian-Yi Li, Li-Sheng Ke, Wen-Ju Yang
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Patent number: 10162928Abstract: A method for designing a semiconductor device includes establishing boundary conditions for a layout of each cell of a plurality of cells, wherein each cell has a plurality of features, and boundary conditions are established based on a proximity of each feature to a cell boundary of a corresponding cell. The method includes determining whether the layout of each cell is colorable based on a number of masks used to manufacture a layer of the semiconductor device, a minimum spacing requirement for the plurality of features, and the established boundary conditions. The method includes forming a layout of the layer of the semiconductor device by abutting a first cell of the plurality of cells with a second cell of the plurality of cells. The method includes reporting the layout of the layer of the semiconductor device as colorable without analyzing the layout of the layer of the semiconductor device.Type: GrantFiled: December 2, 2015Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
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Publication number: 20180341735Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.Type: ApplicationFiled: January 3, 2018Publication date: November 29, 2018Inventors: Yu-Jung CHANG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Wen-Ju YANG
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Patent number: 10140407Abstract: A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns.Type: GrantFiled: November 26, 2014Date of Patent: November 27, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ming Ho, Adari Rama Bhadra Rao, Meng-Kai Hsu, Kuang-Hung Chang, Ke-Ying Su, Wen-Hao Chen, Hsien-Hsin Sean Lee
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Patent number: 10019548Abstract: A method, of generating a modified layout based on an original layout, includes: determining a first set of width bias values of an i-th set of layout patterns which compensate for subtractive process effects, the original layout having N sets of layout patterns corresponding to N masks; determining a second set of width bias values of the i-th set of layout patterns of the original layout which compensate for additive process effects; generating the modified layout based on the first and second sets of width bias values of the i-th set of layout patterns, the order index i of the i-th mask corresponding to an order of the i-th mask being applied during a fabrication process; and fabricating, based on the modified layout, at least one of a semiconductor mask or at least one component in a layer of an inchoate semiconductor integrated circuit.Type: GrantFiled: July 17, 2017Date of Patent: July 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ming Ho, Ke-Ying Su, Hsien-Hsin Sean Lee
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Publication number: 20180150585Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.Type: ApplicationFiled: January 24, 2017Publication date: May 31, 2018Inventors: Tsun-Yu YANG, Wei-Yi HU, Jui-Feng KUAN, Hsien-Hsin Sean LEE, Po-Cheng PAN, Hung-Wen HUANG, Hung-Ming CHEN, Abhishek PATYAL
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Publication number: 20180068049Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.Type: ApplicationFiled: September 2, 2016Publication date: March 8, 2018Inventors: Nien-Yu TSAI, Chin-Chang HSU, Wen-Ju Preet YANG, Hsien-Hsin Sean LEE