Abstract: Described are methods and systems that determine bokeh ratio of a camera, such as a webcam in an information handling system. A focal point and bokeh point are determined for the camera. An image of a Siemens star chart (star chart) is captured by the camera at the bokeh point. The diameter of the captured image of the star chart and diameter of blur circle in the image of the star chart are measured. The ratio of the diameter of the blur circle to the diameter of the captured image of the star chart is correlated to the bokeh ratio of the camera.

Abstract: A semiconductor structure includes a semiconductor die having a first region and a second region is provided. The semiconductor die includes a device layer located in the second region, an insulation material extending over the first and second regions, and metallization structures embedded in the insulation material and electrically connected with the device layer. The metallization structures include passive device structures located in the first region and thermal traces located in the second region, and the passive device structures and the thermal traces include a same material and are co-levelled. The passive device structures are electrically connected with the device layer, and the thermal traces are electrically floating.

Abstract: The invention provides a semiconductor layout pattern including high-voltage devices, which comprises a substrate, wherein a high-voltage device region and an MRAM (magnetic random access memory) region are adjacent to each other, wherein the MRAM region at least comprises a plurality of MRAM cells arranged in an array, wherein each MRAM cell comprises two fin structures parallel to each other and arranged along an X direction, and two gate structures parallel to each other and arranged along a Y direction. A drain metal layer is located between the two gate structures, two source metal layers are located on the other side of the two gate structures, respectively, and an MTJ (magnetic tunneling junction) element is electrically connected with the drain metal layers.

Abstract: Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.

Abstract: A reinforcement learning-based system for adaptively controlling computing performance is provided. The system includes an environment module and an agent module. The environment module is configured to collect environment information from the application environment. Based on the collected environment information, the environment module calculates a reward value using a reward function and then outputs the state data and the reward value to the agent module. The agent module receives the output from the environment module, including the reward value and the state data. Based on the received reward value and state data, the agent module determines a performance adjustment action to take, which is then fed back to the application environment. Upon receiving the performance adjustment action, the application environment executes the performance adjustment operation in response, causing the environment module to collect the updated environment information as a result of the performance adjustment operation.

Abstract: An electronic system includes a first electronic device and a second electronic device. The first electronic device includes a monitoring chip and a hub chip. The monitoring chip is coupled to an upstream port of the hub chip through a first connection and is coupled to the hub chip through a second connection. The second electronic device is configured to couple a downstream port of the hub chip. The monitoring chip is configured to acquire connection information of the second electronic device through the first connection, and acquire status information of the second electronic device through the second connection. The first electronic device is configured to control at least one third electronic device according to the connection information and the status information.

Abstract: A method for large-scale production of a fermentation broth with a high concentration of Bacillus velezensis strain includes the steps of inoculating a seed broth of Bacillus velezensis strain with a bacterial count of 1×107 to 1×109 CFU/mL at 1% to 10% inoculation ratio into a liquid medium, and culturing in a ton-scale fermentation tank at a temperature of 30° C. to 35° C. and at a stirring rate of 40 to 70 rpm for 4 to 5 days, to obtain the fermentation broth having a bacterial count of more than 1×109 CFU/mL. Also provided is a fermentation broth produced by the foregoing production method and a liquid medium for use in the foregoing production method.

Abstract: An encapsulation structure is provided. The encapsulation structure includes a flexible substrate that has an element area and a non-element area. The encapsulation structure also includes multiple electronic elements disposed in the element area. The encapsulation structure further includes multiple light-guiding structures disposed on the electronic elements. The light-guiding structure includes a convex structure and/or a concave structure. The convex structure, in a cross-section, has at least one curved surface, at least two inclined surfaces, or a combination of at least one curved surface and one inclined surface. The concave structure, in a cross-section, has at least one curved surface or at least two inclined surfaces.

Abstract: An electronic device includes a first substrate, a second substrate, organic light emitting diodes, a filter layer, a third substrate, a structure, and a first adhesive element. At least a part of the organic light emitting diodes are disposed on the first substrate. The filter layer is disposed at least on the second substrate. The third substrate is disposed corresponding to the first substrate and the second substrate. The organic light emitting diodes and the structure are disposed under the third substrate. The first adhesive element is disposed between the first substrate and the second substrate, directly contacts the structure, and does not overlap with the organic light emitting diodes. A distance between a bottom surface of the structure and a top surface of the third substrate is different from a minimum distance between one of the organic light emitting diodes and the top surface of the third substrate.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a fin-shaped structure on a substrate, forming a gate material layer on the fin-shaped structure, performing an etching process to pattern the gate material layer for forming a gate structure and a silicon residue, performing an ashing process on the silicon residue, and then performing a cleaning process to transform the silicon residue into a polymer stop layer on a top surface and sidewalls of the fin-shaped structure.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.

Abstract: Described are systems and methods for providing a publisher-subscriber architecture for audio and/or video conferencing. Embodiments of the present disclosure can utilize one edge computing resources associated with each client device participating in the audio and/or video conference. One or more client devices can publish streams to the associated edge computing resources. The streams can then be pushed via a data network to the edge computing resources associated with the subscribing client devices. The subscribing client devices can access and fetch the streams from the edge computing resources, which can be presented on the client devices as part of a conferencing session experience.

Abstract: An integrated circuit includes an inductor that includes a first set of conductors in at least a first metal layer, and a guard ring enclosing the inductor. The guard ring includes a first conductor extending in a first direction, a second conductor extending in a second direction, and a first set of staggered conductors coupled to a first end of the first conductor and a first end of the second conductor. The first set of staggered conductors includes a second set of conductors in a second metal layer, a third set of conductors in a third metal layer and a first set of vias coupling the second set of conductors with the third set of conductors. The third metal layer is above the second metal layer. All metal lines in the second metal layer that are part of the guard ring extend in the first direction.

Abstract: A resin composition is provided. The resin composition comprises: (A) an epoxy resin; (B) a maleimide-triazine resin; and (C) a first flame retardant having a structure of formula (I): wherein, Ar is a C3 to C18 heteroaryl or a C6 to C18 aryl; R1 is H or a C1 to C18 alkyl; and R2 and R3 are independently H, a C1 to C18 alkyl, a C3 to C18 heteroaryl, or a C6 to C18 aryl.

Abstract: A reinforcement learning-based system for adaptively adjusting computing capacity is provided. The system includes an environment module and an agent module. The environment module is configured to collect environment information, including the actual power consumption and one or more power-related metrics, from an application environment. The environment module is further configured to determine a reward value based on the actual power consumption and the expected power consumption, and determine state data based on the one or more power-related metrics. The agent module is configured to receive the reward value and the state data from the environment module, and determine an adjustment action based on the reward value and the state data. The adjustment action involves adjusting the computing capacity and is dynamically executed by the application environment.

Abstract: A one-time programmable memory structure includes semiconductor substrate of a first conductivity type and a fin disposed on the semiconductor substrate. The fin extends along a first direction, wherein the fin includes a first portion and a second portion that is contiguous with the first portion. The first portion and the second portion have different cross-sectional profiles. A gate extends on the fin along a second direction. The gate partially overlaps the first portion of the fin and partially overlaps the second portion of the fin.

Abstract: A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.