Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

Abstract: An electronic device manufacturing system configured to receive, by a processor, input data reflecting a feature related to a manufacturing process of a substrate. The manufacturing system is further configured to generate a characteristic sequence defining a relationship between at least two manufacturing parameters, and determine a relationship between one or more variables related to the feature and the characteristic sequence. The manufacturing system is further configured to determine a weight based on the determined relationship and apply the weight to the feature. The manufacturing system is further configured to train a machine-learning model in view of the weighted feature.

Abstract: A liquid crystal phase-shifting unit includes a first conductive substrate, a second conductive substrate disposed parallel to the first conductive substrate, and a liquid crystal layer disposed between the first conductive substrate and the second conductive substrate. A distance between the first conductive substrate and the second conductive substrate is defined as a liquid crystal cell thickness, which is less than or equal to 5 ?m. The liquid crystal layer includes a cholesteric liquid crystal, which has a pitch. The ratio of the liquid crystal cell thickness to the pitch is greater than or equal to 1. An antenna module including the liquid crystal phase-shifting unit is also provided.

Abstract: An electronic device includes a substrate including a first surface and a second surface opposite to the first surface; a first data line and a second data line disposed on the first surface of the substrate and extending along a first direction; a first electronic unit disposed on the first surface of the substrate; a first control unit disposed on the first surface of the substrate; a first scan line crossing the first data line and the second data line, wherein the first control unit is electrically connected between the first electronic unit and the first scan line; a first switch element disposed on the first surface of the substrate, and comprising a first gate; a first conductive pad disposed on the second surface of the substrate; and a first signal line electrically connected between the first gate of the first switch element and the first conductive pad.

Abstract: An inductive component and a method for fabricating the same are provided. The method includes: filling a mold with a first magnetic powder to form a base layer; forming a cavity in the base layer; inserting a coil corresponding to the cavity; filling the mold with a second magnetic powder to form a cover layer, in which the cover layer fills a space between the cavity and the corresponding coil and covers the base layer and the coil; executing a compression molding process to form a to-be-sliced package and taking the to-be-sliced package out; slicing the to-be-sliced package to obtain a to-be-packaged body; and forming a protective layer and an electrode part electrically connected to the coil on a surface of the to-be-packaged body.

Abstract: A gel-state electrolyte is provided herein. The gel-state electrolyte includes a solvent base; and spherical inorganic nanoparticles dispersed in the solvent base, wherein the spherical inorganic nanoparticles are bonded to each other through an M-O-M structure, wherein M is Ti, Si, Al, Zr, V, Fe, Ni, Zn, or a combination thereof.

Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic component is disposed on a substrate and covered with an encapsulation layer, and a frame body is embedded in the encapsulation layer and protrudes from the substrate. Therefore, the frame body can disperse thermal stress, thereby preventing warping from occurring to the electronic package.

Abstract: A physical vapor deposition (PVD) system is provided. The PVD system includes a PVD chamber defining a PVD volume within which a target material of a target is deposited onto a wafer. The PVD system includes the target in the PVD chamber. The target is configured to overlie the wafer. An edge of the target extends from a first surface of the target to a second surface of the target, opposite the first surface of the target. A first portion of the edge of the target has a first surface roughness. The first portion of the edge of the target extends at most about 6 millimeters from the first surface of the target to a second portion of the edge of the target. The second portion of the edge of the target has a second surface roughness less than the first surface roughness.

Abstract: A circuit test structure includes a chip including a conductive line which traces a perimeter of the chip. The circuit test structure further includes an interposer electrically connected to the chip, wherein the conductive line is over both the chip and the interposer. The circuit test structure further includes a test structure connected to the conductive line. The circuit test structure further includes a testing site, wherein the test structure is configured to electrically connect the testing site to the conductive line.

Abstract: A circular polarizer detection device for detecting a circular polarizer-to-be-detected including a first linear polarizer and a first wave plate is provided. The first linear polarizer has a first transmission axis, the first wave plate has a first fast axis, and there are a preset angle and an error angle between the first transmission axis and the first fast axis. The circular polarizer detection device includes a light source system, a second wave plate and an optical phase demodulation system. A first beam provided by the light source system is converted into a beam-to-be-detected through the circular polarizer-to-be-detected. The beam-to-be-detected enters the rotating second wave plate and then is converted into a second beam. The optical phase demodulation system receives the second beam, generates a phase difference curve, and analyzes a relationship between the rotation angle and the error angle. A circular polarizer detection method is also provided.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Abstract: A method for filling a gap includes: filling a dielectric layer in the gap so that a seam is formed in the dielectric layer, the dielectric layer including two surface portions at two opposite sides of the seam, respectively; introducing a surface modification agent into the seam such that each of the two surface portions has first functional groups and second functional groups; forming a stress layer on the dielectric layer to cover the seam, the stress layer including a material different from that of the dielectric layer; and applying an energy field to permit the two surface portions to bond with each other through reaction between the first functional groups and the second functional groups.

Abstract: A gate oxide layer for a high voltage transistor is formed using methods that avoid thinning in the corners of the gate oxide layer. A recess is formed in a silicon substrate. The exposed surfaces of the recess are thermally oxidized to form a thermal oxide layer of the gate oxide layer. A high temperature oxide layer of the gate oxide layer is then formed within the exposed surfaces of the recess by chemical vapor deposition. The combination of the thermal oxide layer and the high temperature oxide layer results in a gate oxide layer that does not exhibit the double hump phenomenon in the drain current vs. gate voltage curve. The high temperature oxide layer may include a rim that extends out of the recess.

Abstract: An automatic pipe clean system for massage bath equipment includes a bathtub, a water-filling pipe, a water-draining pipe, a suction pipe, a pump pipe, a pump connected between the suction pipe and the pump pipe, an automatic water-filling pipe, a water-filling valve and a controller. The controller is configured to: in a cleaning stage: turn on the pump to allow the water to pass and clean the suction pipe and the pump pipe; and in a drying stage: turn on the pump to allow the water to drain out from the suction pipe and the pump pipe; and turn off the pump.

Abstract: A diode test module and method applicable to the diode test module are provided. A substrate having first conductivity type and an epitaxial layer having second conductivity type on the substrate are formed. A well region having first conductivity type is formed in the epitaxial layer. A first and second heavily doped region having second conductivity type are theoretically formed in the well and connected to a first and second I/O terminal, respectively. Isolation trench is formed there in between for electrical isolation. A monitor cell comprising a third and fourth heavily doped region is provided in a current conduction path between the first and second I/O terminal when inputting an operation voltage. By employing the monitor cell, the invention achieves to determine if the well region is missing by measuring whether a leakage current is generated without additional testing equipment and time for conventional capacitance measurements.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.

Abstract: A semiconductor structure according to the present disclosure includes a substrate, a first base fin and a second base fin arising from the substrate, an isolation structure disposed between the first base fin and the second base fin, first channel members disposed over the first base fin, second channel members disposed over the second base fin, a region isolation feature extending into the substrate, a first gate structure wrapping around each of the first channel members, second gate structure wrapping around each of the second channel members, a first gate cut feature extending through the first gate structure and into the isolation feature, and a second gate cut feature extending though the second gate structure and into the isolation feature. Each of the first gate cut feature and the second gate cut feature are spaced apart from the region isolation feature.

Abstract: The present invention provides a method for preparing an activated carbon, which includes impregnating a carbonaceous material with carbonated water; and exposing the carbonaceous material to microwave radiation to produce the activated carbon.