Abstract: A display device for controlling a privacy region is provided. The display device includes a display unit configured to display images; a touch unit electrically connected to the display unit, wherein the privacy region is determined by the touch unit; and a light control unit electrically connected to the touch unit and configured to control an emitting light angle of the privacy region.

Abstract: A display device and a driving method thereof are provided. In the display device, a display panel has multiple first pixel rows and multiple second pixel rows arranged alternately. In a first time interval, a first gate driver sequentially drives the first pixel rows using a first driving method. In a second time interval, a second gate driver sequentially drives the second pixel rows using the first driving method. In a third time interval, a third gate driver sequentially drives the first pixel rows using a second driving method. In a fourth time interval, a fourth gate driver sequentially drives the second pixel rows using the second driving method. One of the first driving method and the second driving method is a pulse amplitude modulation driving method, and the other of the first driving method and the second driving method is a pulse width modulation driving method.

Abstract: A light-emitting diode includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer, having an upper surface providing a first electrode area containing a pad area and an extended area; a transparent conductive layer over the first semiconductor layer having a first opening to expose a portion of a surface of the first semiconductor layer corresponding to the pad area; a protective layer over the transparent conductive layer having a second opening and a third opening respectively at positions corresponding to the pad area and the extended area, while exposing a portion of the surface of the first semiconductor layer corresponding to the pad area and a portion of a surface of the transparent conductive layer corresponding to the extended area; and a first electrode over the protective layer directly contacting the first semiconductor layer corresponding to the pad area via the first and second openings.

Abstract: Embodiments are directed to a method of optimizing thickness of a target material film deposited on a semiconductor substrate in a semiconductor processing chamber, wherein the semiconductor processing chamber includes a magnetic assembly positioned on the semiconductor processing chamber, the magnetic assembly including a plurality of magnetic columns within the magnetic assembly. The method includes operating the semiconductor processing chamber to deposit a film of target material on a semiconductor substrate positioned within the semiconductor processing chamber, measuring an uniformity of the deposited film, adjusting a position of one or more magnetic columns in the magnetic assembly, and operating the semiconductor processing chamber to deposit the film of the target material after adjusting position of the one or more magnetic columns.

Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

Abstract: A system includes a plurality of semiconductor processing tools; a carrier purge station; a carrier repair station; and an overhead transport (OHT) loop for transporting one or more substrate carriers among the plurality of semiconductor processing tools, the carrier purge station, and the carrier repair station. The carrier purge station is configured to receive a substrate carrier from one of the plurality of semiconductor processing tools, purge the substrate carrier with an inert gas, and determine if the substrate carrier needs repair. The carrier repair station is configured to receive a substrate carrier to be repaired and replace one or more parts in the substrate carrier.

Abstract: A piezoelectric valve may be formed using semiconductor processing techniques such that the piezoelectric valve is biased in a normally closed configuration. Actuation of the piezoelectric valve may be achieved through the use of a piezoelectric-based actuation layer of the piezoelectric valve. The piezoelectric valve may be implemented in various use cases, such as a dispensing valve for precise drug delivery, a relief valve to reduce the occlusion effect in speaker-based devices (e.g., in-ear headphones), a pressure control valve, and/or another type of valve that is configured for microfluidic control, among other examples. The normally closed configuration of the piezoelectric valve enables the piezoelectric valve to operate as a normally closed valve with reduced power consumption.

Abstract: A fireproof material used for a lithium battery module and a method for producing the same are provided. The fireproof material has a stacked structure formed by stacking multiple layers of mesh structures. Each layer of the mesh structures includes a plurality of first fibers and a plurality of second fibers. The first fibers are oxidized fibers, and the second fibers are silicate fibers. Each layer of the mesh structures is formed by interweaving the plurality of first fibers and the plurality of second fibers. The multiple layers of the mesh structures of the fireproof material have a stacked layer number of between 5 layers and 20 layers and a stacked layer thickness of between 0.3 mm and 5 mm. The fireproof material has a density of between 0.05 g/cm3 and 2 g/cm3 and a thermal conductivity of between 0.01 W/(m·K) and 0.8 W/(m·K).

Abstract: A package structure including IPD and method of forming the same are provided. The package structure includes a die, an encapsulant laterally encapsulating the die, a first RDL structure disposed on the encapsulant and the die, an IPD disposed on the first RDL structure and an underfill layer. The IPD includes a substrate, a first connector on a first side of the substrate and electrically connected to the first RDL structure, a guard structure on a second side of the substrate opposite to the first side and laterally surrounding a connector region, and a second connector disposed within the connector region and electrically connected to a conductive via embedded in the substrate. The underfill layer is disposed to at least fill a space between the first side of the IPD and the first RDL structure. The underfill layer is separated from the connector region by the guard structure.

Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Abstract: A manufacturing method of an electronic device is provided by the present disclosure. The method includes: providing a substrate including a non-discarding portion and a discarding portion adjacent to the non-discarding portion; forming a first test wiring extending through the non-discarding portion and the discarding portion; cutting the substrate on a target line, wherein the target line is aligned with a boundary between the non-discarding portion and the discarding portion; performing a first conducting test on the first test wiring; and determining the substrate to be in an off-target cutting state when a result of the first conducting test is a short circuit state, or determining the substrate to be in an on-target cutting state when the result of the first conducting test is an open circuit state.

Abstract: A design method of a photomask structure including the following steps is provided. A layout pattern is provided. The layout pattern includes first to third basic patterns. The second basic pattern is located between the first and third basic patterns and connected to the first and third basic patterns. There is a first jog portion between the first and second basic patterns, there is a second jog portion between the second and third basic patterns, and the first and second jog portions are located at two opposite sides of the layout pattern. The first and second jog portions are moved to align the first and second jog portions with each other and to eliminate the second basic pattern, wherein a first area change amount produced by moving the first jog portion is equal to a second area change amount produced by moving the second jog portion.

Abstract: A low-shrinkage photocurable material is provided in the present disclosure. The low-shrinkage photocurable material includes an acrylonitrile butadiene styrene resin, a carbon black and a dispersant. The carbon black and the dispersant are mixed with the acrylonitrile butadiene styrene resin. The weight percentage of the acrylonitrile butadiene styrene resin is 85%-99.45%, the weight percentage of the carbon black is 0.05%-5%, and the weight percentage of the dispersant is 0.5%-10%.

Abstract: A photomask cleaning tool includes various components to automatically remove a particle from a pellicle, such as a multi-jet nozzle to standardize and control the use of a gas to remove the particle, an ultrasonic probe to loosen the particle from the surface of the pellicle, a plurality of multi-jet nozzles to direct gas toward the particle from different directions, a control system to control the automated blower for various sizes and shapes of photomasks and for optimized particle removal techniques, and/or the like. In this way, the photomask cleaning tool is capable of removing a particle from a pellicle of a photomask in a manner that increases the effectiveness of removing the particle and reduces the likelihood of damage to the pellicle, which would otherwise result in expensive and time-consuming photomask rework.

Abstract: A method for fabricating a semiconductor arrangement includes performing a first etching of a semiconductive structure to expose a first portion of a sidewall of a first layer adjacent the semiconductive structure. The first etching forms a first protective layer on the first portion of the sidewall of the first layer, and the first protective layer is formed from a first accumulation of by-product material formed from an etchant of the first etching interacting with the semiconductive structure. The method includes performing a first flash to remove at least some of the first protective layer.

Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric device including a piezoelectric structure over a substrate. A first conductive structure is disposed on a lower surface of the piezoelectric structure. The first conductive structure includes one or more first movable elements directly contacting the piezoelectric structure. A second conductive structure is disposed on an upper surface of the piezoelectric structure. The second conductive structure includes one or more second movable elements directly contacting the piezoelectric structure. The one or more second movable elements directly overlie the one or more first movable elements.

Abstract: Middle-of-line (MOL) interconnects and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a barrier-free source/drain contact, a barrier-free source/drain via, and a barrier-free gate via disposed in an insulator layer. The barrier-free source/drain is disposed on an epitaxial source/drain, and the barrier-free source/drain contact includes tungsten, molybdenum, or a combination thereof. The barrier-free source/drain via is disposed on the barrier-free source/drain contact and the barrier-free source/drain via includes molybdenum. The barrier-free gate via is disposed on a gate stack disposed adjacent to the epitaxial source/drain, and the barrier-free gate via includes tungsten, molybdenum, or a combination thereof. A width of the barrier-free source/drain via and/or the barrier-free gate via may be less than about 16 nm. The barrier-free source/drain via and/or the barrier-free gate via may be formed at the same time (e.g.