Abstract: A contact structure according to the present disclosure includes a conductive feature, an etch stop layer (ESL) over the conductive feature, a dielectric layer over the ESL, and a contact feature extending through the dielectric layer and the ESL to contact the conductive feature. The dielectric layer includes a low-k dielectric matrix material, and nano-pipes disposed in the low-k dielectric matrix material and configured to reduce a thermal resistance of the dielectric layer.

Abstract: A semiconductor device includes a substrate having a medium-voltage (MV) region and an one time programmable (OTP) capacitor region, a MV device on the MV region, and an OTP capacitor on the OTP capacitor region. Preferably, the MV device includes a first gate dielectric layer on the substrate, a first gate electrode on the first gate dielectric layer, and a shallow trench isolation (STI) adjacent to two sides of the first gate electrode. The OTP capacitor includes a fin-shaped structure on the substrate, a doped region in the fin-shaped structure, a second gate dielectric layer on the doped region, and a second gate electrode on the second gate dielectric layer.

Abstract: A multi-chip integrated package design system includes a model analysis, a 3D model analysis and an electrical simulation. The model analysis obtains a pin connection mode of the designed circuit according to a designed circuit, obtains at least one conductive layer of the designed circuit according to a layer stackup, selects a transmission line model that meets the pin connection mode and at least one conductive layer, substitutes the layer stackup and a design rule into the selected transmission line model to generate an equivalent circuit, generates a corresponding relationship according to the equivalent circuit, and obtains the transmission line length corresponding to a parameter design target according to the corresponding relationship. The 3D model analysis constructs a 3D model of the designed circuit according to the obtained the transmission line length. The electrical simulation determines whether the characteristic parameter of the 3D model meets the parameter design target.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a plurality of conductive interconnects arranged within a dielectric structure having a plurality of inter-level dielectric (ILD) layers stacked onto one another. A heat pipe vertically extends through the plurality of ILD layers. A high thermal conductivity layer is sandwiched between neighboring ones of the plurality of ILD layers. The high thermal conductivity layer laterally extends from over one or more of the plurality of conductive interconnects to the heat pipe.

Abstract: An embodiment records execution of a workflow comprising a skill, the recording generating workflow data. An embodiment selects, using the workflow data, an ontology tree having above a threshold amount of similarity to the workflow. An embodiment constructs, using the ontology tree and the workflow data, a first skill tree corresponding to the workflow. An embodiment integrates, into an existing skill tree of an application, the first skill tree, the integrating resulting in an integrated skill tree of the application. An embodiment executes, responsive to an intent requesting execution of the skill using new data, using the integrated skill tree and the new data, the skill.

Abstract: An electronic device including a display panel and a CPU is provided. The display panel updates displayed images at a refresh rate. The CPU implements a latency monitor, a system resource controller, a display controller, and an application. The latency monitor collects time information related to touch latency. The touch latency is the duration between the time point at which the display panel detects a touch event and the time point at which the display panel displays an image generated by the application in response to said touch event. The display controller informs the system resource controller of the refresh rate. The system resource controller adjusts the resource allocation of the electronic device to cause the touch latency to be lower than a threshold, according to the time information and the refresh rate.

Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of first providing a PUF cell array having a plurality of unit cells, in which each of the unit cells includes a transistor and a first metal-oxide semiconductor capacitor (MOSCAP) and a second MOSCAP coupled to the transistor. Next, a voltage is transmitted through the transistor to the first MOSCAP and the second MOSCAP and whether the first MOSCAP or the second MOSCAP reaches a breakdown is determined.

Abstract: An electrochromic composition is provided, including: a first oxidizable compound with a concentration range of 0.01M-0.5M; a reducible compound with a concentration range of 0.01M-0.5M; an electrolyte with a concentration range of 0.01M-0.

Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

Abstract: A system and method for safe use of an optics assembly with an external light source and an optically coupled optics module is disclosed. The system includes an external light module emitting a continuous wave laser through an output port. An optics module has an input port and a memory. The optics module generates a modulated optical signal. The memory stores the power level of the continuous wave laser signal received by the optics module. An optical jumper is provided for coupling the output port with the input port. A communication bus is coupled between a controller and the external light source module. The controller sets the external light source at a low power level and transitions the external light source to a high power level when the stored power level of the continuous wave laser signal received by the optics module exceeds a predetermined level.

Abstract: A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a buffer layer on a substrate, forming a high velocity layer on the buffer layer, forming a medium velocity layer on the high velocity layer, forming a low velocity layer on the medium velocity layer, forming a piezoelectric layer on the low velocity layer, and forming an electrode on the piezoelectric layer. Preferably, the buffer layer includes silicon oxide, the high velocity layer includes graphene, the medium velocity layer includes silicon oxynitride, and the low velocity layer includes titanium oxide.

Abstract: Systems and methods are provided for determining whether a user has deferred one or more emails. More specifically, a system and method may determine whether an email is likely to have been deferred by a user, perform at least one action on the email determined likely to have been deferred, determine a mode for providing an indication to the user to follow-up with the email determined likely to have been deferred, and cause an indication specific to the email determined likely to have been deferred to be provided to the user. In some instances, the notifications are based on a device associated with the user and/or may be included in at least one of a task management application and/or a calendar application.

Abstract: A processing method for preventing microbiologically influenced corrosion of steel fire sprinkler pipes, includes clearly acid washing a steel pipe, applying anti-rust oil on the interior of the steel pipe, sealing and soldering two ends of the steel pipe to form two soldered and sealed portions on the steel pipe, galvanizing the steel pipe to form a zinc coating layer on the outer surface of the steel pipe, and cutting the two soldered and sealed portions of the steel pipe.

Abstract: A cleaning apparatus for cleaning a surface of a photomask includes a housing defining a chamber, a photomask holder disposed within the chamber, and a gas dispenser disposed within the chamber to direct gas toward the photomask holder. The gas dispenser has two or more gas dispensing outlets. A driver is coupled to at least one of the photomask holder or the gas dispenser to establish relative movement between the photomask holder and the gas dispenser.

Abstract: A gate stack can be etched to form a trench extending through the gate stack, the trench removing a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion. A dielectric material is deposited in the trench to form a dielectric region, the dielectric region having an air gap in the dielectric material. The air gap may extend upward from beneath the gate stack to an area interposed between the end of the first gate stack portion and the end of the second gate stack portion. Contacts to the first gate stack portion and contacts to the second gate stack portion may be formed which are electrically isolated from each other by the dielectric material and air gap formed therein.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: A method of semiconductor fabrication includes forming a plurality of mandrel recesses in a mandrel layer over a hard mask layer, performing a first patterning process on a spacer layer that is deposited over the mandrel layer to form a first opening pattern, performing a second patterning process to etch portions of the mandrel layer to form a second opening pattern, performing a third patterning process to form a third opening pattern in the hard mask layer based on the first opening pattern and the second opening pattern, and forming, through the hard mask layer, metal lines that are in a semiconductor layer under the hard mask layer and that are arranged in a pattern which corresponds to the third opening pattern.

Abstract: A gate stack can be etched to form a trench extending through the gate stack, the trench removing a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion. A dielectric material is deposited in the trench to form a dielectric region, the dielectric region having an air gap in the dielectric material. The air gap may extend upward from beneath the gate stack to an area interposed between the end of the first gate stack portion and the end of the second gate stack portion. Contacts to the first gate stack portion and contacts to the second gate stack portion may be formed which are electrically isolated from each other by the dielectric material and air gap formed therein.

Abstract: Some embodiments relate to a method that includes depositing a first layer of hard mask material over a layer of dielectric material; etching the first layer of the hard mask material, the etched first layer of hard mask material including an etched portion having a first lateral dimension; depositing a second layer of the hard mask material over the first layer of the hard mask material; etching at least a portion of the second layer of the hard mask material, while allowing a remaining portion of the hard mask material, to expose a portion of the layer of the dielectric material that has a second lateral dimension less than the first lateral dimension; and etching a trench into the layer of the dielectric material at the exposed portion of the layer of the dielectric material.

Abstract: A wired communication system includes at least two high-speed communication units compatible with a CAN protocol, the high-speed communication units include: a first CAN transceiver for modulating and transmitting, or receiving and demodulating CAN protocol signals. The first CAN transceiver does not transmit dominant signals in order not to interfere with high-speed signals when the wired communication system is transmitting the high-speed signals; and can transmit signals only after a predetermined time period has elapsed since dominant signaling ceased. The communication system has a default mechanism that allows all the high-speed communication units connected to the same communication medium to know start and end times of transmissions of the high-speed signals for reception and demodulation. All the communication units return to original CAN modes for the arbitration of the next signal transmission.