Abstract: Fabricating a metal-insulator-metal (MIM) capacitor structure includes: forming a patterned metallization layer; disposing a dielectric material on the patterned metallization layer; etching one or more deep trenches through the dielectric material to the patterned metallization layer; depositing a MIM multilayer on the dielectric material and inside the one or more deep trenches formed in the dielectric material; and fabricating at least one three-dimensional MIM (3D-MIM) capacitor comprising a portion of the MIM multilayer deposited inside at least one of the one or more deep trenches; and fabricating at least one second capacitor, including at least one shallow 3D-MIM capacitor comprising a portion of the MIM multilayer deposited inside one or more shallow trenches passing partway through the dielectric material that are shallower than the one or more deep trenches, and/or at least one two-dimensional MIM (2D-MIM) capacitor comprising a portion of the MIM multilayer deposited on the dielectric material.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.

Abstract: An automated optical double-sided inspection apparatus includes a first image-capturing portion, a second image-capturing portion, a platform, a first light-blocking portion, a second light-blocking portion, and a processing portion. The platform carries an external object. When the processing portion operates in a first capturing mode, the second light-blocking portion blocks visible light from passing therethrough, while the first light-blocking portion allows visible light to pass therethrough, so that the first image-capturing portion shoots a first side of the external object through the first light-blocking portion to obtain a first image.

Abstract: A voltage-controlled oscillator (VCO) includes a power supply source, a voltage source, a reference voltage node, first and second transistors, each including a source terminal coupled to the reference voltage node, and first through fourth conductive structures. The first conductive structure includes a first terminal coupled to the power supply source, a first extending portion coupled between the first terminal and a drain terminal of the first transistor, and a second extending portion coupled between the first terminal and a drain terminal of the second transistor, and the second conductive structure includes a second terminal coupled to the voltage source, a third extending portion coupled in series with the third conductive structure between the second terminal and a gate of the first transistor, and a fourth extending portion coupled in series with the fourth conductive structure between the second terminal and a gate of the second transistor.

Abstract: An electronic device including a substrate, an electronic unit, a data line, a control unit, a test pad and a test switch element is provided by the present disclosure. The substrate includes a first surface and a second surface opposite to the first surface, wherein the first surface includes an active area. The electronic unit is disposed on the substrate and located in the active area. The data line is disposed on the substrate. The control unit is disposed on the substrate and located in the active area, and the control unit is electrically connected between the electronic unit and the data line. The test pad is disposed on the second surface of the substrate. The test switch element is disposed on the substrate and located in the active area, and the test switch element is electrically connected between the data line and the test pad.

Abstract: A device includes a microelectromechanical system (MEMS) sensor die comprising a deformable membrane, a MEMS heating element, and a substrate. The MEMS heating element is integrated within a same layer and a same plane as the deformable membrane. The MEMS heating element surrounds the deformable membrane and is separated from the deformable membrane through a trench. The MEMS heating element is configured to generate heat to heat up the deformable membrane. The substrate is coupled to the deformable membrane.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

Abstract: Some implementations herein provide a semiconductor device and methods for forming the semiconductor device. A multi-layer structure of the semiconductor device includes a metal ring structure and a dielectric sidewall structure along interior sidewalls of the metal ring structure. An interconnect structure (e.g., a through silicon via interconnect structure) is along a central interior axis of the metal ring structure. A protective layer is between the interconnect structure and the dielectric sidewall structure. During a deposition operation that fills a cavity with a conductive material to form the interconnect structure, the protective layer may protect the dielectric sidewall structure from damage to improve a quality and/or a reliability of the semiconductor device.

Abstract: An information handling system camera supports plural filters selectively inserted between a lens and an image sensor by plural actuators disposed around the perimeter of the lens and image sensor so that the actuators do not add to the vertical height of the camera. Plural actuators support simultaneous insertion of plural filters that cooperate to offer day, night, distance detection and camera focus distance and zoom levels by refractive manipulation of light passing through a neutral density (transparent) piece of material of an increased thickness.

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

Abstract: A power connector module is provided, including a housing, an electrical connector unit disposed in a first space of the housing, and a socket unit disposed in a second space of the housing. The glue is received in the first space, and a gate plate is disposed on a diaphragm of the housing to prevent the glue from flowing into the second space.

Abstract: A semiconductor device includes a substrate, a heat dissipation dielectric layer, a conductive interconnect structure, and a blocking dielectric layer. The heat dissipation dielectric layer is disposed on the substrate and has a thermal conductivity greater than 10 W/mK. The conductive interconnect structure is disposed in the heat dissipation dielectric layer. The blocking dielectric layer is disposed in the heat dissipation dielectric layer to isolate the conductive interconnect structure from the heat dissipation dielectric layer.

Abstract: An embodiment of the disclosure provides an electronic device including multiple units. Each unit in the units includes multiple primary bonding regions and at least one reserved bonding region. Each reserved bonding region is connected to the primary bonding regions. The number of the at least one reserved bonding region is less than the number of primary bonding regions.

Abstract: Embodiments are directed to a method of optimizing thickness of a target material film deposited on a semiconductor substrate in a semiconductor processing chamber, wherein the semiconductor processing chamber includes a magnetic assembly positioned on the semiconductor processing chamber, the magnetic assembly including a plurality of magnetic columns within the magnetic assembly. The method includes operating the semiconductor processing chamber to deposit a film of target material on a semiconductor substrate positioned within the semiconductor processing chamber, measuring an uniformity of the deposited film, adjusting a position of one or more magnetic columns in the magnetic assembly, and operating the semiconductor processing chamber to deposit the film of the target material after adjusting position of the one or more magnetic columns.

Abstract: A fireproof material used for a lithium battery module and a method for producing the same are provided. The fireproof material has a stacked structure formed by stacking multiple layers of mesh structures. Each layer of the mesh structures includes a plurality of first fibers and a plurality of second fibers. The first fibers are oxidized fibers, and the second fibers are silicate fibers. Each layer of the mesh structures is formed by interweaving the plurality of first fibers and the plurality of second fibers. The multiple layers of the mesh structures of the fireproof material have a stacked layer number of between 5 layers and 20 layers and a stacked layer thickness of between 0.3 mm and 5 mm. The fireproof material has a density of between 0.05 g/cm3 and 2 g/cm3 and a thermal conductivity of between 0.01 W/(m·K) and 0.8 W/(m·K).

Abstract: A manufacturing method of an electronic device is provided by the present disclosure. The method includes: providing a substrate including a non-discarding portion and a discarding portion adjacent to the non-discarding portion; forming a first test wiring extending through the non-discarding portion and the discarding portion; cutting the substrate on a target line, wherein the target line is aligned with a boundary between the non-discarding portion and the discarding portion; performing a first conducting test on the first test wiring; and determining the substrate to be in an off-target cutting state when a result of the first conducting test is a short circuit state, or determining the substrate to be in an on-target cutting state when the result of the first conducting test is an open circuit state.

Abstract: A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.

Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

Abstract: A semiconductor arrangement includes a heat source above an interconnect layer and below a heat conductor. The heat conductor is coupled to a heat sink by a thermally conductive bonding layer. Heat from the heat source is conducted through the heat conductor in a direction opposite the direction of the interconnect layer, through the thermally conductive bonding layer, and to a heat sink. The heat conductor includes an arrangement of dielectric layers, dummy metal layers, and dummy VIA layers.

Abstract: The present disclosure, in some embodiments, relates to a capacitor structure. The capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A lower electrode is arranged along sidewalls and an upper surface of the lower dielectric structure, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is arranged along outermost sidewalls of the upper electrode. The spacer includes a first upper surface arranged along a first side of the upper electrode and a second upper surface arranged along an opposing second side of the upper electrode. The first upper surface has a different width than the second upper surface.