Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, forming a doped layer on the substrate of the non-MOSCAP region and the first fin-shaped structure on the MOSCAP region, removing the doped layer on the non-MOSCAP region, and then performing an anneal process to drive dopants from the doped layer into the first fin-shaped structure.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material. A second semiconductor material is disposed on the substrate. A doped region is between the substrate and a part of the second semiconductor material. The second semiconductor material includes a projection extending outward from a surface of the second semiconductor material and towards the photodiode region. The projection extends through the doped region.

Abstract: A printed circuit board comprising a differential microstrip pair including a neck-down area and an ultraviolet glue coating a portion of the neck-down area of the differential microstrip pair to control an impedance of the differential microstrip pair.

Abstract: A package includes a first package component; a second package component bonded to the first package component by a first plurality of solder connectors; and a first plurality of spacer connectors extending from the first package component to the second package component. A diameter of a spacer connector the first plurality of spacer connectors is larger than a height of a solder connector of the first plurality of solder connectors, and the first plurality of spacer connectors comprises a different material than the first plurality of solder connectors.

Abstract: A semiconductor processing system is provided. The semiconductor processing system includes a first chamber arranged to perform a first semiconductor process; a second chamber arranged to perform a second semiconductor process; a cooling chamber having a pedestal; and a plurality of non-contact temperature sensors mounted in the cooling chamber, and arranged to measure a temperature of a wafer disposed on the pedestal. In one aspect, the first chamber is arranged to transfer the wafer to the cooling chamber upon completion of the first semiconductor process in the first chamber. In another aspect, the cooling chamber is arranged to measure the temperature of the wafer in the cooling chamber and arranged to transfer the wafer to the second chamber when the temperature of wafer is at a target temperature, or pause processing of the wafer when the temperature of the wafer is not at the target temperature.

Abstract: An auto framing method is applied to a camera apparatus with an image receiver and a screen. The auto framing method includes receiving a detection image from the image receiver, computing a distance between the image receiver and an identification feature of the detection image, switching a framing mode of the screen into a normal mode or a single mode in accordance with a comparison result of the distance and a predefined distance threshold, setting a preset step count and a preset frame interval to compute a coordinate variation of the identification feature when position difference between a current focus area and a cropping area generated by the framing mode conforms to a predefined difference condition, and utilizing the coordinate variation to acquire an area variation of the cropping area, and scaling the cropping area to a target resolution for displaying on the screen in accordance with the area variation.

Abstract: A memory structure includes: first and second word lines; a high-k dielectric layer disposed on the first and second word lines; a channel layer disposed on the high-k dielectric layer and comprising a semiconductor material; first and second source electrodes electrically contacting the channel layer; a first drain electrode disposed on the channel layer between the first and second source electrodes; a memory cell electrically connected to the first drain electrode; and a bit line electrically connected to the memory cell.

Abstract: A memory device includes a bottom electrode contact, a magnetic tunnel junction pattern, a protection insulating layer, a first capping layer, an interlayer insulating layer, and a second capping layer. The magnetic tunnel junction pattern is over the bottom electrode contact. The protection insulating layer surrounds the magnetic tunnel junction pattern. The first capping layer surrounds the protection insulating layer. The interlayer insulating layer surrounds the first capping layer. The second capping layer is over the first capping layer and the interlayer insulating layer.

Abstract: An information platform for providing an earthquake early warning of a large area is disclosed. The large area includes a plurality of small districts, different sets of the plurality of small districts form different large districts according to geographical locations so as to make up the large area, and the information platform is both connected with a plurality of on-site earthquake early warning stations and the plurality of small districts through a cloud network. The plurality of on-site earthquake early warning stations are located in the large districts respectively, each of the plurality of on-site earthquake early warning stations is configured to obtain a real-time seismic longitudinal wave measurement data, obtain a real-time seismic transverse wave feature prediction value corresponding to the real-time seismic longitudinal wave measurement data, and transmit the real-time seismic transverse wave feature prediction value.

Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.

Abstract: A pixel circuit of a display panel includes a light emitting device, a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor has a gate terminal, a drain terminal and a source terminal. The second transistor is coupled to the gate terminal of the first transistor. The third transistor is coupled to the source terminal of the first transistor. The fourth transistor, coupled to the drain terminal of the first transistor and the light emitting device, includes a gate terminal, a drain terminal and a source terminal. The gate terminal of the fourth transistor is coupled to a gate line on the display panel. The drain terminal of the fourth transistor is coupled to the gate line. The source terminal of the fourth transistor is coupled to the drain terminal of the first transistor.

Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.

Abstract: A circuit of a resonant power converter comprising: a high-side switch and a low-side switch, coupled to form a half-bridge switching circuit which is configured to switch a transformer for generating an output voltage; a high-side drive circuit, generating a high-side drive signal coupled to drive the high-side switch in response to a high-side control signal; a bias voltage, coupled to a bootstrap diode and a bootstrap capacitor providing a power source from the bootstrap capacitor for the high-side drive circuit; wherein the high-side drive circuit generates the high-side drive signal with a fast slew rate to turn on the high-side switch when the high-side switch is to be turned on with soft-switching; the high-side drive circuit generates the high-side drive signal with a slow slew rate to turn on the high-side switch when the high-side switch is to be turned on without soft-switching.

Abstract: Some embodiments relate to an integrated circuit device incorporating a dual via structure for through-chip connections. The integrated circuit device includes a substrate, at least one dielectric layer disposed over a frontside surface of the substrate, and a plurality of metal layers residing in the at least one dielectric layer. The integrated circuit device also includes a first via structure and a second via structure. The first via structure includes a plurality of vias. The first via structure is electrically connected to one of the plurality of metal layers and extends through the frontside surface of the substrate. The second via structure extends from a backside surface of the substrate opposite the frontside surface into the substrate and contacts the first via structure.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: An embodiment high-density capacitor includes a bottom electrode having a plurality of non-concentric cylindrical portions, a top electrode including a plurality of vertical portions and a surrounding portion, and a dielectric layer separating the top electrode from the bottom electrode. Each of the plurality of non-concentric cylindrical portions includes an inner shell and an outer shell and each of the plurality of vertical portions is vertically surrounded by the inner shell of a respective cylindrical portion of the bottom electrode. The surrounding portion of the top electrode respectively vertically surrounds each of the plurality of non-concentric cylindrical portions of the bottom electrode such that adjacent non-concentric cylindrical portions of the bottom electrode are separated from one another by the surrounding portion of the top electrode. At least some of the plurality of non-concentric cylindrical portions of the bottom electrode include a spatial distribution having a hexagonal symmetry.

Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, then a cladding layer is formed to cover the electronic element, and a shielding layer is formed on the cladding layer to cover the electronic element. The cladding layer is bonded to a shielding structure, and the shielding structure is located between the shielding layer and the electronic element, so as to prevent the electronic element from being subjected to external electromagnetic interference via multiple shielding mechanisms of the shielding structure and the shielding layer.

Abstract: A 3D printer includes a frame, a carrier, a nozzle and a detection device. The carrier is fixed to the frame. The nozzle is movably disposed on the frame. The detection device includes a piezoelectric ceramic sheet and a position detector. The piezoelectric ceramic sheet is in contact with the carrier. The position detector is disposed on the nozzle.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

Abstract: An integrated chip including a semiconductor substrate having a first side and a second side, opposite the first side. A first transistor and a second transistor are along the first side of the semiconductor substrate. A dielectric structure including a plurality of dielectric layers is under the first side of the semiconductor substrate. A first metal line is within the dielectric structure. A second metal line is within the dielectric structure and under the first metal line. A first metal via extends between the first metal line and the second metal line. A through-substrate via (TSV) extends from the second side of the semiconductor substrate, through the semiconductor substrate between the first transistor and the second transistor, to the first metal line and the second metal line.