Abstract: Described are methods and systems for auto framing an object of interest. A webcam of an information handling system captures a full field of view image that has a region of interest (ROI) that includes a pointing element, such as an active pen, user finger, or other such object. The ROI also includes the object of interest. An auto-framing AI/ML model detects the ROI and the pointing element and auto-frames the object of interest to which the pointing element is directed to.

Abstract: A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.

Abstract: An electrochemical plating apparatus for depositing a conductive material on a wafer includes a cell chamber. The plating solution is provided from a bottom of the cell chamber into the cell chamber. A plurality of openings passes through a sidewall of the cell chamber. A flow regulator is arranged with each of the plurality of openings configured to regulate an overflow amount of the plating solution flowing out through the each of the plurality of openings. The electrochemical plating apparatus further comprises a controller to control the flow regulator such that overflow amounts of the plating solution flowing out through the plurality of openings are substantially equal to each other.

Abstract: A plating system is provided. The plating system includes an electroplating chamber defining a plating region within which a wafer is plated. The electroplating chamber includes an inlet configured to introduce plating solution into the plating region of the electroplating chamber. The electroplating chamber includes an outlet configured to remove the plating solution from the plating region of the electroplating chamber. The plating system includes a barrier configured to inhibit removal of the plating solution from the plating region.

Abstract: An apparatus for electroplating includes a cup configured to support a substrate, and a cone including at least three distance measuring devices arranged on a lower surface thereof and facing the substrate. Each distance measuring device is configured to transmit a laser pulse towards the substrate, the laser pulse impinging the substrate, receive a reflected laser pulse from the substrate, calculate a turnaround time of the laser pulse, and calculate a distance between the distance measuring device and the substrate using the turnaround time for determining an inclination of the substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a source/drain structure, a contact structure, a glue layer, a barrier layer, and a silicide layer. The contact structure is over the source/drain structure. The glue layer surrounds the contact structure. The barrier layer is formed on at least a portion of a sidewall surface of the contact structure. The silicide layer is between the source/drain structure and the contact structure, and the silicide layer is in direct contact with the glue layer. The bottom surface of the glue layer is lower than the top surface of the source/drain structure and the bottom surface of the barrier layer.

Abstract: The invention discloses a vessel automatic berthing wireless charging integrated system and operating method thereof. The invention comprises a charging barge and at least one vessel. The charging barge comprises a power, a distribution board and a locking module control system, and every vessel comprises an automatic pilot system, a vessel controlling system and a wireless power receiving module. A bow berthing module of the present invention moors the vessel. After a guiding structure of the bow berthing module straightly aligns bow direction of the vessel, a wireless power supplying module of a side berthing module matches with the wireless power receiving module then charges the vessel.

Abstract: An illumination lamp system having automatic switching function for sterilization is disclosed. It contains a plurality of germicidal lighting lamp assemblies, a personnel counter, a data receiving indicator, and an ultraviolet indicator. Each germicidal lighting lamp assembly includes a lamp panel, an infrared human body sensor and a control module. The control module includes a power conversion unit, a synchronization interface, a startup circuit, a first microcontroller, and an output and input connection interface. Because the infrared human body sensor can detect the appearance of people in real time, with a synchronous voltage to switch emitting between illumination LED strips and ultraviolet germicidal light sources, in addition to effectively expanding the disinfection area, it can also safely adjust the type of light to achieve the automatic switching function for sterilization.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

Abstract: A method includes forming a dielectric layer over a conductive feature, and etching the dielectric layer to form an opening. The conductive feature is exposed through the opening. The method further includes forming a tungsten liner in the opening, wherein the tungsten liner contacts sidewalls of the dielectric layer, depositing a tungsten layer to fill the opening, and planarizing the tungsten layer. Portions of the tungsten layer and the tungsten liner in the opening form a contact plug.

Abstract: A micro light-emitting diode package structure and a forming method thereof are provided. The micro light-emitting diode package structure includes micro light-emitting diode dies, a light-transmitting layer, a first insulating layer, redistribution layers, and conductive elements. The micro light-emitting diode dies are disposed side by side and each includes an electrode surface, a light-emitting surface, and side surfaces. The electrode surface and the light-emitting surface are opposite to each other, and the side surfaces are between them. The light-transmitting layer covers the light-emitting surface and the side surfaces. The first insulating layer is under the micro light-emitting diode dies and in direct contact with the electrode surface. The redistribution layers are disposed under the first insulating layer and pass through the first insulating layer to electrically connect the electrode surface.

Abstract: A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.

Abstract: A package structure is provided. The package structure includes a semiconductor chip and a first dielectric layer over the semiconductor chip and extending across opposite sidewalls of the semiconductor chip. The package structure also includes a conductive layer over the first dielectric layer, and the conductive layer has multiple first protruding portions extending into the first dielectric layer. The package structure further includes a second dielectric layer over the first dielectric layer and the conductive layer. The second dielectric layer has multiple second protruding portions extending into the first dielectric layer. Each of the first protruding portions and the second protruding portions is thinner than the first dielectric layer.

Abstract: An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.

Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.

Abstract: A semiconductor device includes a semiconductor layered structure, an electrode unit, and an anti-adsorption layer. The electrode unit is disposed on an electrode connecting region of the semiconductor layered structure, and is a multi-layered structure. The anti-adsorption layer is disposed on a top surface of the electrode unit opposite to the semiconductor layered structure. Also disclosed herein is a light-emitting system including the semiconductor device.

Abstract: A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.

Abstract: A manufacturing method for a semiconductor structure is provided. First active areas, a second active area, and a third active area are formed. A first dielectric layer is formed on the active areas. A patterned region that includes a cavity region and a dielectric region is formed in the first dielectric layer, and the cavity region surrounds the dielectric region. A filling layer is formed in the cavity region. Multiple first contact holes and at least one second contact hole that penetrate the first dielectric layer are formed. Each first contact hole exposes a portion of the corresponding first active area, and the second contact hole replaces the dielectric region and exposes a portion of the second active area. Metal layers are filled in to the first contact holes and the second contact hole.