Patents by Inventor Hsien-Ming Lee

Hsien-Ming Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210007646
    Abstract: A test strip for sampling a bodily fluid may include multiple layers of a substrate material, an adhesive between at least some of the multiple layers, and a microfluidic channel formed between at least some of the multiple layers. The test strip may further include multiple electrodes on one of the multiple layers, positioned and partially exposed within the microfluidic channel, an additional material positioned at or near an entrance to the microfluidic channel, to selectively limit the flow of at least one of bubbles or debris into the microfluidic channel, and at least one exit port in at least one of the multiple layers to allow for release of pressure from the test strip. In some embodiments, the test strip is a saliva analysis test strip. In some embodiments, the test strip includes multiple exit ports to prevent blockage of sample flow.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 14, 2021
    Inventors: Thanh Cong Nguyen, Efstratios Skafidas, Duc Hau Huynh, Michael Erlichster, Duc Phuong Nguyen, Hsien Ming, Gursharan Chana, Ting Ting Lee, Chathurika Darshani Abeyrathne, You Liang, Trevor John Kilpatrick, Michael Luther, Alan Dayvault Luther
  • Publication number: 20210005322
    Abstract: A method of measuring an analyte in a bodily fluid sample and combining measurement data from multiple users may involve initiating a wireless connection between a handheld analyzer and a smart computing device on which an analyte analysis application has been downloaded and inserting a test strip into the handheld analyzer. The method may further involve collecting a sample of a bodily fluid on the test strip, measuring, with the handheld analyzer, a concentration of at least one analyte in the sample, wirelessly communicating the measured concentration from the handheld analyzer to the smart computing device, and displaying the measured concentration on the smart computing device. Finally, the method may involve transmitting the measured concentration to a database and organizing data including the measured concentration and at least one additional measured analyte concentration from at least one additional user on the database.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 7, 2021
    Inventors: Duc Hau Huynh, Michael Erlichster, Thanh Cong Nguyen, Duc Phuong Nguyen, Efstratios Skafidas, Hsien Ming, Gursharan Chana, Ting Ting Lee, Chathurika Darshani Abeyrathne, You Liang, Trevor John Kilpatrick, Michael Luther, Alan Dayvault Luther
  • Patent number: 10872769
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
  • Patent number: 10854459
    Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu, Hsin-Yun Hsu, Pin-Hsuan Yeh
  • Publication number: 20200335404
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 22, 2020
    Inventors: Da-Yuan LEE, Hung-Chin CHUNG, Hsien-Ming LEE, Kuan-Ting LIU, Syun-Ming JANG, Weng CHANG, Wei-Jen LO
  • Patent number: 10804161
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Publication number: 20200287014
    Abstract: Provided is a semiconductor device including a first n-type fin field effect transistor (FinFET) and a second n-type FinFET. The first FinFET includes a first work function layer. The first work function layer includes a first portion of a first layer. The second n-type FinFET includes a second work function layer. The second work function layer includes a second portion of the first layer and a first portion of a second layer underlying the second portion of the first layer. A thickness of the first work function layer is less than a thickness of the second work function layer. A method of manufacturing the semiconductor device is also provided.
    Type: Application
    Filed: May 27, 2020
    Publication date: September 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Fen Chien, Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu
  • Publication number: 20200266297
    Abstract: A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate within a first region and includes a first gate electrode. The first gate electrode includes a first filter layer between and in contact with a first conductive layer and a second conductive layer. The second transistor is disposed on the substrate within a second region and includes a second gate electrode. The second gate electrode includes a second filter layer between and in contact with a third conductive layer and a fourth conductive layer. The first transistor and the second transistor have a same conductive type, a first threshold voltage of the first transistor is lower than a second threshold voltage of the second transistor, and a first thickness of the first filter layer is larger than a second thickness of the second filter layer.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Chang Wei, Chia-Lin Hsu, Hsien-Ming Lee, Ji-Cheng Chen
  • Patent number: 10707318
    Abstract: Provided is a semiconductor device including a fin-type field effect transistor (FinFET). The first FinFET includes a first gate structure and the first gate structure includes a first work function layer. The first work function layer includes a first layer and a second layer. The first layer is disposed over the second layer. The second layer includes a base material and a dopant doped in the base material. The dopant comprises Al, Ta, W, or a combination thereof. The first layer and the second layer comprise different materials. A method of manufacturing the semiconductor device is also provided.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Fen Chien, Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu
  • Patent number: 10699966
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Da-Yuan Lee, Hung-Chin Chung, Hsien-Ming Lee, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang, Wei-Jen Lo
  • Patent number: 10644153
    Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and a filter layer, and strain layers. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. The gate stack includes a gate dielectric layer, a work function layer and a metal filling layer. The gate dielectric layer is disposed on the semiconductor fin. The work function layer is disposed on the gate dielectric layer. The metal filling layer is over the work function layer. The filter layer is disposed between the work function layer and the metal filling layer to prevent or decrease penetration of diffusion atoms. The strain layers are beside the gate stack. A material of the filter layer is different from a material of the work function layer and a material of the metal filling layer.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Chang Wei, Chia-Lin Hsu, Hsien-Ming Lee, Ji-Cheng Chen
  • Publication number: 20200135471
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: December 30, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
  • Patent number: 10626899
    Abstract: A clamping fixture includes a body, a connector, a first clasp, at least one first elastic member and a lock. The connector is movable relative to the body along a first direction. The first clasp includes a first fastener and is disposed at one end of the connector. The at least one first elastic member is configured to apply force to the body and the connector along the first direction. The lock includes a second fastener. The first clasp and the lock are coupled through the first fastener and the second fastener.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: April 21, 2020
    Assignee: ABILITY ENTERPRISE CO., LTD.
    Inventors: Hao-Chung Lien, Chia-Wei Fu, Hsien-Ming Lee
  • Publication number: 20200105895
    Abstract: A method of forming a semiconductor device includes forming a gate electrode in a wafer. The formation of the gate electrode includes depositing a work-function layer, after the work-function layer is deposited, performing a treatment on the wafer, wherein the treatment is performed by soaking the wafer using a silicon-containing gas; after the treatment, forming a metal capping layer over the work-function layer; and depositing a filling metal over the metal capping layer.
    Type: Application
    Filed: July 1, 2019
    Publication date: April 2, 2020
    Inventors: Tsung-Ta Tang, Yi-Ting Wang, Chung Ta Chen, Hsien-Ming Lee
  • Patent number: 10535523
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
  • Publication number: 20200000722
    Abstract: Disclosed herein are novel synthetic polypeptides and uses thereof in the preparation of liposomes. According to embodiments of the present disclosure, the synthetic polypeptide comprises a membrane lytic motif, a masking motif, and a linker configured to link the membrane lytic motif and the masking motif. The linker is cleavable by a stimulus, such as, light, protease, or phosphatase. Once being coupled to a liposome, the exposure to the stimulus cleaves the linker that results in the separation of the masking motif from the membrane lytic motif, which in turn exerts membrane lytic activity on the liposome that leads to the collapse of the intact structure of the liposome, and releases the agent encapsulated in the liposome to the target site. Also disclosed herein are methods of diagnosing or treating a disease in a subject by use of the present liposomes.
    Type: Application
    Filed: June 28, 2019
    Publication date: January 2, 2020
    Applicant: Academia Sinica
    Inventors: Hsien-Ming LEE, Hua-De GAO, Jia-Lin HONG, Chih-Yu KUO, Cheng-Bang JIAN
  • Patent number: 10515807
    Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Fen Chien, Chih-Hsiang Fan, Hsiao-Kuan Wei, Pohan Kung, Hsien-Ming Lee
  • Publication number: 20190385855
    Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 19, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Fen CHIEN, Chih-Hsiang FAN, Hsiao-Kuan WEI, Pohan KUNG, Hsien-Ming LEE
  • Patent number: 10395370
    Abstract: A method and a wearable apparatus for disease diagnosis are provided. The method is applied to the wearable apparatus with an image capturing unit and a display unit. In this method, a plurality of input images in a field of view of the wearable apparatus are captured by using the image capturing unit, wherein each of the input images contains an array of pixels. The variations of the pixel values in a time domain are analyzed. The pixel variations within a specific frequency range are magnified and the magnified pixel variations are added onto the original ones to generate an output image. The output image is overlapped with a current image in the field of view of the wearable apparatus and displayed on the display unit.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: August 27, 2019
    Assignee: National Taiwan University
    Inventors: Hao-Ming Hsiao, Hsien-Li Kao, Kuang-Huei Lee, Dian-Ru Li
  • Publication number: 20190145444
    Abstract: A clamping fixture includes a body, a connector, a first clasp, at least one first elastic member and a lock. The connector is movable relative to the body along a first direction. The first clasp includes a first fastener and is disposed at one end of the connector. The at least one first elastic member is configured to apply force to the body and the connector along the first direction. The lock includes a second fastener. The first clasp and the lock are coupled through the first fastener and the second fastener.
    Type: Application
    Filed: October 11, 2018
    Publication date: May 16, 2019
    Inventors: Hao-Chung LIEN, Chia-Wei FU, Hsien-Ming LEE