Abstract: A nitrogen-containing semiconductor device including a first type doped semiconductor layer, a multiple quantum well layer and a second type doped semiconductor layer is provided. The multiple quantum well layer includes barrier layers and well layers, and the well layers and the barrier layers are arranged alternately. The multiple quantum well layer is located between the first type doped semiconductor layer and the second type doped semiconductor layer, and one of the well layers of the multiple quantum well layer is connected to the second type doped semiconductor layer.

Abstract: A nitrogen-containing semiconductor device including a substrate, a first AlGaN buffer layer, a second AlGaN buffer layer and a semiconductor stacking layer is provided. The first AlGaN buffer layer is disposed on the substrate, and the second AlGaN buffer layer is disposed on the first AlGaN buffer layer. A chemical formula of the first AlGaN buffer layer is AlxGa1-xN, wherein 0?x?1. The first AlGaN buffer layer is doped with at least one of oxygen having a concentration greater than 5×1017 cm?3 and carbon having a concentration greater than 5×1017 cm?3. A chemical formula of the second AlGaN buffer layer is AlyGa1-yN, wherein 0?y?1. The semiconductor stacking layer is disposed on the second AlGaN buffer layer.

Abstract: A transistor including a substrate, a source, a drain, an active portion, a fin-shaped gate, and an insulation layer is provided. The source is located on the substrate. The drain is located on the substrate. The active portion connects the source and the drain. The fin-shaped gate wraps the active portion. A first portion of the insulation layer separates the fin-shaped gate from the active portion, a second portion of the insulation layer separates the fin-shaped gate from the substrate, a third portion of the insulation layer separates the fin-shaped gate from the source and from the drain, and a fourth portion of the insulation layer is located on a surface of the fin-shaped gate facing away from the active portion. Here, the insulation layer is integrally formed.

Abstract: A manufacturing method of a transistor is provided, and the method includes: providing a base; forming a fin-shaped gate on the base; covering the fin-shaped gate with an insulation layer; providing a substrate; forming a partially cured sol-gel on the substrate; inserting the fin-shaped gate into the partially cured sol-gel, so that a portion of the fin-shaped gate is uncovered by the partially cured sol-gel; after inserting the fin-shaped gate into the partially cured sol-gel, curing the partially cured sol-gel; and processing a portion of the partially cured sol-gel not overlapping with the fin-shaped gate to increase conductivity of the portion of the partially cured sol-gel.

Abstract: A nitrogen-containing semiconductor device including a first type doped semiconductor layer, a multiple quantum well layer and a second type doped semiconductor layer is provided. The multiple quantum well layer includes barrier layers and well layers, and the well layers and the barrier layers are arranged alternately. The multiple quantum well layer is located between the first type doped semiconductor layer and the second type doped semiconductor layer, and one of the well layers of the multiple quantum well layer is connected to the second type doped semiconductor layer.

Abstract: A nitrogen-containing semiconductor device including a substrate, a first AlGaN buffer layer, a second AlGaN buffer layer and a semiconductor stacking layer is provided. The first AlGaN buffer layer is disposed on the substrate, and the second AlGaN buffer layer is disposed on the first AlGaN buffer layer. A chemical formula of the first AlGaN buffer layer is AlxGa1-xN, wherein 0?x?1. The first AlGaN buffer layer is doped with at least one of oxygen having a concentration greater than 5×1017 cm?3 and carbon having a concentration greater than 5×1017 cm?3. A chemical formula of the second AlGaN buffer layer is AlyGa1-yN, wherein 0?y?1. The semiconductor stacking layer is disposed on the second AlGaN buffer layer.

Abstract: Methods of fabricating emitter regions of solar cells are described. Methods of forming layers on substrates of solar cells, and the resulting solar cells, are also described.

Abstract: A multiple quantum well structure includes a plurality of well-barrier sets arranged along a direction. Each of the well-barrier sets includes a barrier layer, at least one intermediate level layer, and a well layer. A bandgap of the barrier layer is greater than an average bandgap of the intermediate level layer, and the average bandgap of the intermediate level layer is greater than a bandgap of the well layer. The barrier layers, the intermediate level layers, and the well layers of the well-barrier sets are stacked by turns. Thicknesses of at least parts of the well layers in the direction gradually decrease along the direction, and thicknesses of at least parts of the intermediate level layers in the direction gradually increase along the direction. A method for manufacturing a multiple quantum well structure is also provided.

Abstract: A multilayer anti-reflection structure for a backside contact solar cell. The anti-reflection structure may be formed on a front side of the backside contact solar cell. The anti-reflection structure may include a passivation level, a high optical absorption layer over the passivation level, and a low optical absorption layer over the high optical absorption layer. The passivation level may include silicon dioxide thermally grown on a textured surface of the solar cell substrate, which may be an N-type silicon substrate. The high optical absorption layer may be configured to block at least 10% of UV radiation coming into the substrate. The high optical absorption layer may comprise high-k silicon nitride and the low optical absorption layer may comprise low-k silicon nitride.

Abstract: A multiple quantum well structure includes a plurality of well-barrier sets arranged along a direction. Each of the well-barrier sets includes a barrier layer, at least one intermediate level layer, and a well layer. A bandgap of the barrier layer is greater than an average bandgap of the intermediate level layer, and the average bandgap of the intermediate level layer is greater than a bandgap of the well layer. The barrier layers, the intermediate level layers, and the well layers of the well-barrier sets are stacked by turns. Thicknesses of at least parts of the well layers in the direction gradually decrease along the direction, and thicknesses of at least parts of the intermediate level layers in the direction gradually increase along the direction. A method for manufacturing a multiple quantum well structure is also provided.

Abstract: A system for substrate deposition is disclosed. The system includes a wafer pallet and an anode. The wafer pallet has a bottom and a top. The top of the wafer pallet is configured to hold a substrate wafer. The anode has a substantially fixed position relative to the wafer pallet and is configured to move with the wafer pallet through the deposition chamber. The anode is electrically isolated from the substrate wafer.

Abstract: A manufacturing method of a transistor is provided, and the method includes: providing a base; forming a fin-shaped gate on the base; covering the fin-shaped gate with an insulation layer; providing a substrate; forming a partially cured sol-gel on the substrate; inserting the fin-shaped gate into the partially cured sol-gel, so that a portion of the fin-shaped gate is uncovered by the partially cured sol-gel; after inserting the fin-shaped gate into the partially cured sol-gel, curing the partially cured sol-gel; and processing a portion of the partially cured sol-gel not overlapping with the fin-shaped gate to increase conductivity of the portion of the partially cured sol-gel.

Abstract: A transistor including a substrate, a source, a drain, an active portion, a fin-shaped gate, and an insulation layer is provided. The source is located on the substrate. The drain is located on the substrate. The active portion connects the source and the drain. The fin-shaped gate wraps the active portion. A first portion of the insulation layer separates the fin-shaped gate from the active portion, a second portion of the insulation layer separates the fin-shaped gate from the substrate, a third portion of the insulation layer separates the fin-shaped gate from the source and from the drain, and a fourth portion of the insulation layer is located on a surface of the fin-shaped gate facing away from the active portion. The insulation layer is integrally formed. A manufacturing method of a transistor is also provided.

Abstract: A solar cell includes a crystalline silicon semiconductor substrate, an intrinsic amorphous silicon semiconductor layer, an amorphous silicon semiconductor layer and a transparent conductive layer. The crystalline silicon semiconductor substrate possesses a first doped type and a trench is formed thereon to form an enclosed area to define a first electrode region in the enclosed area and a second electrode region out of the enclosed area. The intrinsic amorphous silicon semiconductor layer, the amorphous silicon semiconductor layer and the transparent conductive layer are formed sequentially on the crystalline silicon semiconductor substrate and in the trench. Having discontinuity in the trench, the amorphous silicon semiconductor layer, the amorphous silicon semiconductor layer and the transparent conductive layer provide an isolation function between the previously defined first and second electrode regions.

Abstract: A solar cell includes a crystalline silicon semiconductor substrate, an intrinsic amorphous silicon semiconductor layer, an amorphous silicon semiconductor layer and a transparent conductive layer. The crystalline silicon semiconductor substrate possesses a first doped type and a trench is formed thereon to form an enclosed area to define a first electrode region in the enclosed area and a second electrode region out of the enclosed area. The intrinsic amorphous silicon semiconductor layer, the amorphous silicon semiconductor layer and the transparent conductive layer are formed sequentially on the crystalline silicon semiconductor substrate and in the trench. Having discontinuity in the trench, the amorphous silicon semiconductor layer, the amorphous silicon semiconductor layer and the transparent conductive layer provide an isolation function between the previously defined first and second electrode regions.

Abstract: A microbubble ultrasound contrast agent for external use is provided. The microbubble ultrasound contrast agent applied externally can safely and efficiently enhance the permeation and absorption of the drug or small molecules in the local region of the body surface. A method of preparing the microbubble ultrasound contrast agent and a method of enhancing percutaneous absorption of a chemical or small molecules through a topical region of a biological body surface are provided.

Abstract: A multilayer anti-reflection structure for a backside contact solar cell. The anti-reflection structure may be formed on a front side of the backside contact solar cell. The anti-reflection structure may include a passivation level, a high optical absorption layer over the passivation level, and a low optical absorption layer over the high optical absorption layer. The passivation level may include silicon dioxide thermally grown on a textured surface of the solar cell substrate, which may be an N-type silicon substrate. The high optical absorption layer may be configured to block at least 10% of UV radiation coming into the substrate. The high optical absorption layer may comprise high-k silicon nitride and the low optical absorption layer may comprise low-k silicon nitride.

Abstract: A multilayer anti-reflection structure for a backside contact solar cell. The anti-reflection structure may be formed on a front side of the backside contact solar cell. The anti-reflection structure may include a passivation level, a high optical absorption layer over the passivation level, and a low optical absorption layer over the high optical absorption layer. The passivation level may include silicon dioxide thermally grown on a textured surface of the solar cell substrate, which may be an N-type silicon substrate. The high optical absorption layer may be configured to block at least 10% of UV radiation coming into the substrate. The high optical absorption layer may comprise high-k silicon nitride and the low optical absorption layer may comprise low-k silicon nitride.

Abstract: A system for substrate deposition is disclosed. The system includes a wafer pallet and an anode. The wafer pallet has a bottom and a top. The top of the wafer pallet is configured to hold a substrate wafer. The anode has a substantially fixed position relative to the wafer pallet and is configured to move with the wafer pallet through the deposition chamber. The anode is electrically isolated from the substrate wafer.

Abstract: A system for substrate deposition. The system includes a wafer pallet and an anode. The wafer pallet has a bottom and a top. The top of the wafer pallet is configured to hold a substrate wafer. The anode has a substantially fixed position relative to the wafer pallet and is configured to move with the wafer pallet through the deposition chamber. The anode is electrically isolated from the substrate wafer.