Patents by Inventor Hsin-Hsien Lu
Hsin-Hsien Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180350634Abstract: A semiconductor device is manufactured using a cleaning process. The cleaning process utilizes a semiconductor manufacturing tool that has a wet cleaning section and a plasma cleaning section. The semiconductor device is placed within a wet cleaning chamber within the wet cleaning section, where a wet cleaning process is performed. Once completed, and without breaking atmosphere, the semiconductor device is removed from the wet cleaning section and placed within a plasma cleaning chamber within the plasma cleaning section. A plasma clean is then performed.Type: ApplicationFiled: August 1, 2017Publication date: December 6, 2018Inventors: Meng-Hsien Li, Hsin-Hsien Lu
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Patent number: 9852899Abstract: Some embodiments are directed to a wafer polishing tool. The wafer polishing tool includes a first polisher, a second polisher downstream of the first polisher, a third polisher downstream of the second polisher, and a fourth polisher downstream of the third polisher. The first polisher receives a wafer having a front side and a back side with integrated circuit component devices disposed on the front side of the wafer, and polishes a center region on the back side of the wafer. The second polisher receives the wafer via transporting equipment and buffs the center region of the back side of the wafer. The third polisher receives the wafer via the transporting equipment and polishes a back side edge region of the wafer. The fourth polisher receives the wafer via the transporting equipment and buffs the back side edge region of the wafer.Type: GrantFiled: January 17, 2017Date of Patent: December 26, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shen-Nan Lee, Teng-Chun Tsai, Hsin-Hsien Lu, Chang-Sheng Lin, Kuo-Cheng Lien, Kuo-Yin Lin, Wen-Kuei Liu, Yu-Wei Chou
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Publication number: 20170182628Abstract: Some embodiments relate to a method of using a polishing system. In this method, a wafer is secured in a carrier head. The carrier head includes a housing, which includes a retaining ring recess, enclosing the wafer. A retaining ring is positioned in the retaining ring recess. The retaining ring surrounds the wafer, and has a hardness ranging from about 5 shore A to about 80 shore D. The wafer is pressed against a polishing pad, and at least one of the carrier head or the polishing pad is moved relative to the other.Type: ApplicationFiled: March 15, 2017Publication date: June 29, 2017Inventors: Chang-Sheng Lin, Hsin-Hsien Lu
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Publication number: 20170133218Abstract: A wafer cleaning apparatus includes a polishing unit used in chemical mechanical polishing (CMP) of a wafer and a cleaning dispensing unit arranged to direct cleaning fluids toward a far edge of the wafer after the CMP of the wafer. A wafer cleaning method includes CMP of a wafer by a polishing unit and directing cleaning fluids toward a far edge of the wafer after the CMP of the wafer by a cleaning dispensing unit. Another method can include CMP, applying deionized water, and applying pH adjuster having a pH range from about 2 to about 13.Type: ApplicationFiled: January 26, 2017Publication date: May 11, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Hsien LU, Ting-Kui CHANG, Jung-Tsan TSAI
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Publication number: 20170125237Abstract: Some embodiments are directed to a wafer polishing tool. The wafer polishing tool includes a first polisher, a second polisher downstream of the first polisher, a third polisher downstream of the second polisher, and a fourth polisher downstream of the third polisher. The first polisher receives a wafer having a front side and a back side with integrated circuit component devices disposed on the front side of the wafer, and polishes a center region on the back side of the wafer. The second polisher receives the wafer via transporting equipment and buffs the center region of the back side of the wafer. The third polisher receives the wafer via the transporting equipment and polishes a back side edge region of the wafer. The fourth polisher receives the wafer via the transporting equipment and buffs the back side edge region of the wafer.Type: ApplicationFiled: January 17, 2017Publication date: May 4, 2017Inventors: Shen-Nan Lee, Teng-Chun Tsai, Hsin-Hsien Lu, Chang-Sheng Lin, Kuo-Cheng Lien, Kuo-Yin Lin, Wen-Kuei Liu, Yu-Wei Chou
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Patent number: 9597771Abstract: A carrier head includes a housing configured to enclose a wafer, wherein the housing includes a retaining ring recess. The carrier head includes a retaining ring positioned in the retaining ring recess, the retaining ring configured to surround the wafer. The retaining ring has a hardness ranging from about 5 shore A to about 80 shore D. A method of using a polishing system includes securing a wafer in a carrier head. The carrier head includes a housing enclosing the wafer, wherein the housing includes a retaining ring recess. The carrier head includes a retaining ring in the retaining ring recess. The retaining ring has a hardness ranging from about 5 shore A to about 80 shore D. The method includes pressing the wafer against a polishing pad, and moving at least one of the carrier head or the polishing pad relative to the other.Type: GrantFiled: December 19, 2013Date of Patent: March 21, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chang-Sheng Lin, Hsin-Hsien Lu
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Patent number: 9601409Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metal contact that eliminates RC opens caused by metal dishing during chemical mechanical polishing. The method is performed by depositing a sacrificial UV/thermal decomposition layer (UTDL) above an inter-level dielectric (ILD) layer. A metal contact is formed that extend through the ILD layer and the sacrificial UTDL. A chemical mechanical polishing (CMP) process is performed to generate a planar surface comprising the sacrificial UTDL. The sacrificial UTDL is then removed through an ultraviolet exposure or a thermal anneal, so that the metal contact protrudes from the ILD layer.Type: GrantFiled: December 29, 2014Date of Patent: March 21, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Hsien Lu, Chia-Fang Tsai
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Patent number: 9576789Abstract: A wafer cleaning apparatus includes a polishing unit used in chemical mechanical polishing (CMP) of a wafer and a cleaning dispensing unit arranged to direct cleaning fluids toward a far edge of the wafer after the CMP of the wafer. A wafer cleaning method includes CMP of a wafer by a polishing unit and directing cleaning fluids toward a far edge of the wafer after the CMP of the wafer by a cleaning dispensing unit. Another method can include CMP, applying deionized water, and applying pH adjuster having a pH range from about 2 to about 13.Type: GrantFiled: January 29, 2013Date of Patent: February 21, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Hsien Lu, Ting-Kui Chang, Jung-Tsan Tsai
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Patent number: 9559021Abstract: A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads.Type: GrantFiled: March 4, 2016Date of Patent: January 31, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shen-Nan Lee, Teng-Chun Tsai, Hsin-Hsien Lu, Chang-Sheng Lin, Kuo-Cheng Lien, Kuo-Yin Lin, Wen-Kuei Liu, Yu-Wei Chou
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Patent number: 9466501Abstract: Provided is a method of planarizing a semiconductor device. A dielectric layer is formed over a substrate. A plurality of openings is formed in the dielectric layer. The openings have varying distribution densities. The openings are filled with a metal material. A first chemical-mechanical-polishing (CMP) process is performed to remove portions of the metal material over the dielectric layer. Thereafter, a sacrificial layer is formed over the dielectric layer and the metal material. The sacrificial layer has a planar surface. The sacrificial layer is formed through one of: a spin-on process or a flowable chemical vapor deposition (FCVD) process. A second CMP process is then performed to remove the sacrificial layer and portions of the dielectric layer and the metal material therebelow. The second CMP process uses a slurry configured to have a substantially similar polishing selectivity between the sacrificial layer, the dielectric layer, and the metal material.Type: GrantFiled: September 5, 2014Date of Patent: October 11, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Hsien Lu, Chang-Sheng Lin
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Patent number: 9434047Abstract: A retainer ring for chemical-mechanical polishing or other processes includes an outside ring and an inside ring that is attached to the outside ring. The inside ring is softer than the outside ring in hardness.Type: GrantFiled: December 14, 2012Date of Patent: September 6, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Lien, Hsin-Hsien Lu
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Patent number: 9415479Abstract: A polishing pad for polishing a substrate. The pad comprises a layer of material having an upper polishing surface and a lower surface interfacing with a proximate platen, the material comprising a mixture of a conductive polymer distributed in a structure of a dielectric polymeric material using predetermined relationships. Additional embodiments provide a pad having a layer of dielectric polymeric material with an upper polishing surface and a lower surface interfacing with a proximate platen. A first set of grooves filled with a conductive polymer extends from the upper polishing surface to the lower surface, the first set of grooves filled with a conductive polymer. A second set of shallower grooves provide for slurry flow over the upper polishing surface. The first and/or second set of grooves are provided in a predetermined pattern.Type: GrantFiled: February 8, 2013Date of Patent: August 16, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chang-Sheng Lin, Hsin-Hsien Lu
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Publication number: 20160190023Abstract: A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads.Type: ApplicationFiled: March 4, 2016Publication date: June 30, 2016Inventors: Shen-Nan Lee, Teng-Chun Tsai, Hsin-Hsien Lu, Chang-Sheng Lin, Kuo-Cheng Lien, Kuo-Yin Lin, Wen-Kuei Liu, Yu-Wei Chou
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Patent number: 9287127Abstract: A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20 k or finer grit or non-abrasive pads.Type: GrantFiled: February 17, 2014Date of Patent: March 15, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shen-Nan Lee, Teng-Chun Tsai, Hsin-Hsien Lu, Chang-Sheng Lin, Kuo-Cheng Lien, Kuo-Yin Lin, Wen-Kuei Liu, Yu-Wei Chou
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Publication number: 20150235858Abstract: A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads.Type: ApplicationFiled: February 17, 2014Publication date: August 20, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shen-Nan Lee, Teng-Chun Tsai, Hsin-Hsien Lu, Chang-Sheng Lin, Kuo-Cheng Lien, Kuo-Yin Lin, Wen-Kuei Liu, Yu-Wei Chou
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Publication number: 20150174727Abstract: A carrier head includes a housing configured to enclose a wafer, wherein the housing includes a retaining ring recess. The carrier head includes a retaining ring positioned in the retaining ring recess, the retaining ring configured to surround the wafer. The retaining ring has a hardness ranging from about 5 shore A to about 80 shore D. A method of using a polishing system includes securing a wafer in a carrier head. The carrier head includes a housing enclosing the wafer, wherein the housing includes a retaining ring recess. The carrier head includes a retaining ring in the retaining ring recess. The retaining ring has a hardness ranging from about 5 shore A to about 80 shore D. The method includes pressing the wafer against a polishing pad, and moving at least one of the carrier head or the polishing pad relative to the other.Type: ApplicationFiled: December 19, 2013Publication date: June 25, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chang-Sheng LIN, Hsin-Hsien LU
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Publication number: 20150170940Abstract: A brush cleaning apparatus includes a wafer support configured to support a wafer, and at least one cleaning brush moveable relative to the wafer support. The at least one cleaning brush has opposite first and second sides, and, on the first side, a planar cleaning surface configured to come into contact with the wafer supported by the wafer support to remove contaminants from the wafer.Type: ApplicationFiled: December 13, 2013Publication date: June 18, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chang-Sheng LIN, Hsin-Hsien LU
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Publication number: 20150115471Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metal contact that eliminates RC opens caused by metal dishing during chemical mechanical polishing. The method is performed by depositing a sacrificial UV/thermal decomposition layer (UTDL) above an inter-level dielectric (ILD) layer. A metal contact is formed that extend through the ILD layer and the sacrificial UTDL. A chemical mechanical polishing (CMP) process is performed to generate a planar surface comprising the sacrificial UTDL. The sacrificial UTDL is then removed through an ultraviolet exposure or a thermal anneal, so that the metal contact protrudes from the ILD layer.Type: ApplicationFiled: December 29, 2014Publication date: April 30, 2015Inventors: Hsin-Hsien Lu, Chia-Fang Tsai
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Patent number: 8921150Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metal contact that eliminates RC opens caused by metal dishing during chemical mechanical polishing. The method is performed by depositing a sacrificial UV/thermal decomposition layer (UTDL) above an inter-level dielectric (ILD) layer. A metal contact is formed that extend through the ILD layer and the sacrificial UTDL. A chemical mechanical polishing (CMP) process is performed to generate a planar surface comprising the sacrificial UTDL. The sacrificial UTDL is then removed through an ultraviolet exposure or a thermal anneal, so that the metal contact protrudes from the ILD layer.Type: GrantFiled: December 6, 2012Date of Patent: December 30, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Hsien Lu, Chia-Fang Tsai
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Publication number: 20140377954Abstract: Provided is a method of planarizing a semiconductor device. A dielectric layer is formed over a substrate. A plurality of openings is formed in the dielectric layer. The openings have varying distribution densities. The openings are filled with a metal material. A first chemical-mechanical-polishing (CMP) process is performed to remove portions of the metal material over the dielectric layer. Thereafter, a sacrificial layer is formed over the dielectric layer and the metal material. The sacrificial layer has a planar surface. The sacrificial layer is formed through one of: a spin-on process or a flowable chemical vapor deposition (FCVD) process. A second CMP process is then performed to remove the sacrificial layer and portions of the dielectric layer and the metal material therebelow. The second CMP process uses a slurry configured to have a substantially similar polishing selectivity between the sacrificial layer, the dielectric layer, and the metal material.Type: ApplicationFiled: September 5, 2014Publication date: December 25, 2014Inventors: Hsin-Hsien Lu, Chang-Sheng Lin