Patents by Inventor Hsin-Hsien Lu
Hsin-Hsien Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8889544Abstract: The disclosure provides mechanisms of performing metal chemical-mechanical polishing (CMP) without significant loss of copper and a dielectric film of damascene structures. The mechanisms use a metal CMP stop layer made of a low-k dielectric film with a porogen, which significantly reduces the removal rate of the metal CMP stop layer by metal CMP. The metal CMP stop layer is converted into a porous low-k dielectric film after a cure (or curing) to remove or convert the porogen. The low-k value, such as equal to or less than about 2.6, of the metal CMP stop layer makes the impact of using of the metal CMP stop layer on RC delay from minimum to none. Further the CMP stop layer protects the porous low-k dielectric film underneath from exposure to water, organic compounds, and mobile ions in the CMP slurry.Type: GrantFiled: February 16, 2011Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Hsu Wu, Hsin-Hsien Lu, Tien-I Bao, Shau-Lin Shue
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Publication number: 20140256134Abstract: Provided is a method of planarizing a semiconductor device. A dielectric layer is formed over a substrate. A plurality of openings is formed in the dielectric layer. The openings have varying distribution densities. The openings are filled with a metal material. A first chemical-mechanical-polishing (CMP) process is performed to remove portions of the metal material over the dielectric layer. Thereafter, a sacrificial layer is formed over the dielectric layer and the metal material. The sacrificial layer has a planar surface. The sacrificial layer is formed through one of: a spin-on process or a flowable chemical vapor deposition (FCVD) process. A second CMP process is then performed to remove the sacrificial layer and portions of the dielectric layer and the metal material therebelow. The second CMP process uses a slurry configured to have a substantially similar polishing selectivity between the sacrificial layer, the dielectric layer, and the metal material.Type: ApplicationFiled: March 8, 2013Publication date: September 11, 2014Inventors: Hsin-Hsien Lu, Chang-Sheng Lin
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Patent number: 8828875Abstract: Provided is a method of planarizing a semiconductor device. A dielectric layer is formed over a substrate. A plurality of openings is formed in the dielectric layer. The openings have varying distribution densities. The openings are filled with a metal material. A first chemical-mechanical-polishing (CMP) process is performed to remove portions of the metal material over the dielectric layer. Thereafter, a sacrificial layer is formed over the dielectric layer and the metal material. The sacrificial layer has a planar surface. The sacrificial layer is formed through one of: a spin-on process or a flowable chemical vapor deposition (FCVD) process. A second CMP process is then performed to remove the sacrificial layer and portions of the dielectric layer and the metal material therebelow. The second CMP process uses a slurry configured to have a substantially similar polishing selectivity between the sacrificial layer, the dielectric layer, and the metal material.Type: GrantFiled: March 8, 2013Date of Patent: September 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Hsien Lu, Chang-Sheng Lin
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Publication number: 20140227945Abstract: A method and system for planarizing or polishing a semiconductor wafer. The system includes a carrier adaptable to hold a semiconductor wafer, a polishing pad, and a platen having a substantially planar surface in contact with the polishing pad, the planar surface having a distribution of holes. The distributed holes are operatively connected to a vacuum system providing a vacuum pressure to hold the polishing pad against the platen during operation of the system. Relative movement between the carrier and polishing pad acts to planarize a surface of the wafer.Type: ApplicationFiled: February 8, 2013Publication date: August 14, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Sheng LIN, Hsin-Hsien LU
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Publication number: 20140213056Abstract: A wafer cleaning apparatus includes a polishing unit used in chemical mechanical polishing (CMP) of a wafer and a cleaning dispensing unit arranged to direct cleaning fluids toward a far edge of the wafer after the CMP of the wafer. A wafer cleaning method includes CMP of a wafer by a polishing unit and directing cleaning fluids toward a far edge of the wafer after the CMP of the wafer by a cleaning dispensing unit. Another method can include CMP, applying deionized water, and applying pH adjuster having a pH range from about 2 to about 13.Type: ApplicationFiled: January 29, 2013Publication date: July 31, 2014Applicant: Taiwan Semiconductor Manufacturing Co., LTD.Inventors: Hsin-Hsien LU, Ting-Kui CHANG, Jung-Tsan TSAI
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Publication number: 20140159244Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metal contact that eliminates RC opens caused by metal dishing during chemical mechanical polishing. The method is performed by depositing a sacrificial UV/thermal decomposition layer (UTDL) above an inter-level dielectric (ILD) layer. A metal contact is formed that extend through the ILD layer and the sacrificial UTDL. A chemical mechanical polishing (CMP) process is performed to generate a planar surface comprising the sacrificial UTDL. The sacrificial UTDL is then removed through an ultraviolet exposure or a thermal anneal, so that the metal contact protrudes from the ILD layer.Type: ApplicationFiled: December 6, 2012Publication date: June 12, 2014Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Hsin-Hsien Lu, Chia-Fang Tsai
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Patent number: 8348719Abstract: Embodiments of a polisher for chemical mechanical planarization. The polisher includes a polishing pad structure containing a first reactant therein, and a second reactant in a polishing environment over the polishing pad structure. The first reactant and the second reactant react endothermically upon contact when polishing a wafer surface between the polishing pad structure and the polishing environment.Type: GrantFiled: March 23, 2007Date of Patent: January 8, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Hsien Lu, Liang-Guang Chen, Tien-I Bao, Shau-Lin Shue
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Patent number: 8252682Abstract: A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer.Type: GrantFiled: February 12, 2010Date of Patent: August 28, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ku-Feng Yang, Weng-Jin Wu, Hsin-Hsien Lu, Chia-Lin Yu, Chu-Sung Shih, Fu-Chi Hsu, Shau-Lin Shue
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Publication number: 20120205814Abstract: The disclosure provides mechanisms of performing metal chemical-mechanical polishing (CMP) without significant loss of copper and a dielectric film of damascene structures. The mechanisms use a metal CMP stop layer made of a low-k dielectric film with a porogen, which significantly reduces the removal rate of the metal CMP stop layer by metal CMP. The metal CMP stop layer is converted into a porous low-k dielectric film after a cure (or curing) to remove or convert the porogen. The low-k value, such as equal to or less than about 2.6, of the metal CMP stop layer makes the impact of using of the metal CMP stop layer on RC delay from minimum to none. Further the CMP stop layer protects the porous low-k dielectric film underneath from exposure to water, organic compounds, and mobile ions in the CMP slurry.Type: ApplicationFiled: February 16, 2011Publication date: August 16, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Hsu WU, Hsin-Hsien LU, Tien-I BAO, Shau-Lin SHUE
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Patent number: 8021566Abstract: An apparatus and method suitable for the pre-conditioning of a polishing pad on a CMP apparatus prior to the polishing of production wafers on the apparatus. The apparatus includes a pre-conditioning arm on which is mounted an ingot of suitable material. In use, the ingot is pressed against the polishing surface of the rotating polishing pad for a selected period of time to increase the temperature of the polishing surface by friction. The pre-conditioned polishing pad facilitates uniform polishing rates of production semiconductor wafers subsequently polished on the apparatus.Type: GrantFiled: August 2, 2006Date of Patent: September 20, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Che Chuang, Wen-Chih Chiou, Hsin-Hsien Lu, Liang-Guang Chen
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Publication number: 20110198721Abstract: A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer.Type: ApplicationFiled: February 12, 2010Publication date: August 18, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ku-Feng YANG, Weng-Jin Wu, Hsin-Hsien Lu, Chia-Lin Yu, Chu-Sung Shih, Fu-Chi Hsu, Shau-Lin Shue
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Publication number: 20080233839Abstract: Embodiments of a polisher for chemical mechanical planarization. The polisher includes a polishing pad structure containing a first reactant therein, and a second reactant in a polishing environment over the polishing pad structure. The first reactant and the second reactant react endothermically upon contact when polishing a wafer surface between the polishing pad structure and the polishing environment.Type: ApplicationFiled: March 23, 2007Publication date: September 25, 2008Inventors: Hsin-Hsien Lu, Liang-Guang Chen, Tien-I Bao, Shau-Lin Shue
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Publication number: 20060270237Abstract: An apparatus and method suitable for the pre-conditioning of a polishing pad on a CMP apparatus prior to the polishing of production wafers on the apparatus. The apparatus includes a pre-conditioning arm on which is mounted an ingot of suitable material. In use, the ingot is pressed against the polishing surface of the rotating polishing pad for a selected period of time to increase the temperature of the polishing surface by friction. The pre-conditioned polishing pad facilitates uniform polishing rates of production semiconductor wafers subsequently polished on the apparatus.Type: ApplicationFiled: August 2, 2006Publication date: November 30, 2006Inventors: Chia-Che Chuang, Wen-Chih Chiou, Hsin-Hsien Lu, Liang-Guang Chen
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Patent number: 7105446Abstract: An apparatus and method suitable for the pre-conditioning of a polishing pad on a CMP apparatus prior to the polishing of production wafers on the apparatus. The apparatus includes a pre-conditioning arm on which is mounted an ingot of suitable material. In use, the ingot is pressed against the polishing surface of the rotating polishing pad for a selected period of time to increase the temperature of the polishing surface by friction. The pre-conditioned polishing pad facilitates uniform polishing rates of production semiconductor wafers subsequently polished on the apparatus.Type: GrantFiled: September 4, 2003Date of Patent: September 12, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Che Chuang, Wen-Chih Chiou, Hsin-Hsien Lu, Liang-Guang Chen
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Publication number: 20060112971Abstract: A method for cleaning a semiconductor wafer surface comprises sweeping the semiconductor wafer surface and applying a first cleaning solution having a first pH, stop applying the first cleaning solution and applying a first rinsing solution to the semiconductor wafer surface, the first rinsing solution having a second pH that is significantly different from the first pH, sweeping the semiconductor wafer surface and applying a second cleaning solution having a third pH, and stop applying the second cleaning solution and applying a second rinsing solution to the semiconductor wafer surface, the second rinsing solution having a fourth pH that is significantly different from the third pH.Type: ApplicationFiled: November 30, 2004Publication date: June 1, 2006Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Hsin Kuo, Hsin-Hsien Lu, Ying-Ho Chen, Syun-Ming Jang
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Patent number: 6962869Abstract: A method of protecting a low k dielectric layer that is preferably comprised of a material containing Si, O, C, and H is described. The dielectric layer is subjected to a gas plasma that is generated from a CXHY gas which is preferably ethylene. Optionally, hydrogen may be added to the CXHY gas. Another alternative is a two step plasma process involving a first plasma treatment of CXHY or CXHY combined with H2 and a second plasma treatment with H2. The modified dielectric layer provides improved adhesion to anti-reflective layers and to a barrier metal layer in a damascene process. The modified dielectric layer also has a low CMP rate that prevents scratch defects and an oxide recess from occurring next to the metal layer on the surface of the damascene stack. The plasma treatments are preferably done in the same chamber in which the dielectric layer is deposited.Type: GrantFiled: October 15, 2002Date of Patent: November 8, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tien-I Bao, Hsin-Hsien Lu, Lih-Ping Li, Chung-Chi Ko, Aaron Song, Syun-Ming Jang
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Publication number: 20050170980Abstract: A method for the cleaning of wafers typically during a chemical mechanical polishing (CMP) process. The method includes polishing a material layer on a wafer in sequential polishing steps, rinsing the wafer using a novel surfactant composition solution after at least one of the polishing steps and rinsing of the wafer using deionized water, respectively. The surfactant composition solution imparts a generally hydrophilic character to a hydrophobic material layer such as a high-k dielectric layer on the wafer. Consequently, the layer is rendered amenable to cleaning by deionized water, thereby significantly enhancing the removal of particles from the layer and reducing the number of defects related to the CMP process.Type: ApplicationFiled: January 30, 2004Publication date: August 4, 2005Inventors: Hsin-Hsien Lu, Han-Hsin Kuo, Ying-Ho Chen, Syum-Ming Jang
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Publication number: 20050051266Abstract: An apparatus and method suitable for the pre-conditioning of a polishing pad on a CMP apparatus prior to the polishing of production wafers on the apparatus. The apparatus includes a pre-conditioning arm on which is mounted an ingot of suitable material. In use, the ingot is pressed against the polishing surface of the rotating polishing pad for a selected period of time to increase the temperature of the polishing surface by friction. The pre-conditioned polishing pad facilitates uniform polishing rates of production semiconductor wafers subsequently polished on the apparatus.Type: ApplicationFiled: September 4, 2003Publication date: March 10, 2005Inventors: Chia-Che Chuang, Wen-Chih Chiou, Hsin-Hsien Lu, Liang-Guang Chen
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Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer
Patent number: 6770570Abstract: A semiconductor device 100 includes a low-k dielectric insulator 104. In the preferred embodiment, a low-k dielectric material 104 is deposited. This material 104 is then cured using a plasma cure step. The cure process causes the density of the top portion 106 of layer 104 to be increased. The higher density portion 106, however, also has a higher dielectric constant. As a result, the dielectric constant of the layer 104 can be reduced by removing this higher density portion 106. This leads to a lower dielectric constant (e.g., less than about 3) of the bulk film.Type: GrantFiled: November 15, 2002Date of Patent: August 3, 2004Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lih-Ping Li, Hsin-Hsien Lu, Syun-Ming Jang -
Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer
Publication number: 20040097099Abstract: A semiconductor device 100 includes a low-k dielectric insulator 104. In the preferred embodiment, a low-k dielectric material 104 is deposited. This material 104 is then cured using a plasma cure step. The cure process causes the density of the top portion 106 of layer 104 to be increased. The higher density portion 106, however, also has a higher dielectric constant. As a result, the dielectric constant of the layer 104 can be reduced by removing this higher density portion 106. This leads to a lower dielectric constant (e.g., less than about 3) of the bulk film.Type: ApplicationFiled: November 15, 2002Publication date: May 20, 2004Inventors: Lih-Ping Li, Hsin-Hsien Lu, Syun-Ming Jang