Patents by Inventor HSIU-WEN HSUEH

HSIU-WEN HSUEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout
    Patent number: 9218448
    Abstract: A method comprises generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions comprises a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the spacing values.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: December 22, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming Ho, C. Y. Chen, Hsiu-Wen Hsueh, Jun-Fu Huang, Shao-Heng Chou
  • RESISTIVE CAPACITANCE DETERMINATION METHOD FOR MULTIPLE-PATTERNING-MULTIPLE SPACER INTEGRATED CIRCUIT LAYOUT
    Publication number: 20150205905
    Abstract: A method comprises generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions comprises a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the spacing values.
    Type: Application
    Filed: January 20, 2014
    Publication date: July 23, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming HO, C, Y. CHEN, Hsiu-Wen HSUEH, Jun-Fu HUANG, Shao-Heng CHOU
  • METAL OXIDE THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF
    Publication number: 20120112180
    Abstract: The instant disclosure relates to a metal oxide thin film transistor having a threshold voltage modification layer. The thin film transistor includes a gate electrode, a dielectric layer formed on the gate electrode, an active layer formed on the dielectric layer, a source electrode and a drain electrode disposed separately on the active layer, and a threshold voltage modulation layer formed on the active layer in direct contact with the back channel of the transistor. The threshold voltage modulation layer and the active layer have different work functions so that the threshold voltage modulation layer modulates the threshold voltage of devices and improve the performance of the transistor.
    Type: Application
    Filed: December 2, 2010
    Publication date: May 10, 2012
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: HSIAO-WEN ZAN, CHUANG-CHUANG TSAI, WEI-TSUNG CHEN, HSIU-WEN HSUEH