Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.

Abstract: The present disclosure relates to a method includes generating ions with an ion source of an ion implantation apparatus based on an ion implantation recipe. The method includes accelerating the generated ions based on an ion energy setting in the ion implantation recipe and determining an energy spectrum of the accelerated ions. The method also includes analyzing a relationship between the determined energy spectrum and the ion energy setting. The method further includes adjusting at least one parameter of a final energy magnet (FEM) of the ion implantation apparatus based on the analyzed relationship.

Abstract: An ion implantation system comprising: a sample platform; an ion gun; an electrostatic linear accelerator; a direct current (DC) final energy magnet (FEM); and a processor. The processor is programmed to control: a wafer acceptance test instrument, a DC recipe calculator, a DC real energy calculator, and a tool energy shift verifier. The wafer acceptance test instrument is configured to apply a wafer acceptance test (WAT) recipe to a test sample on the sample platform. The DC recipe calculator is configured to calculate a recipe for the DC FEM. The DC real energy calculator is configured to calculate a real energy of the DC FEM. The tool energy shift verifier is configured to verify a tool energy shift of the DC FEM. The ion implantation system is configured to tune the DC FEM based on the verified tool energy shift, and obtain a peak magnetic field of the DC FEM.

Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

Abstract: In a method of manufacturing a semiconductor device, a support layer is formed over a substrate. A patterned semiconductor layer made of a first semiconductor material is formed over the support layer. A part of the support layer under a part of the semiconductor layer is removed, thereby forming a semiconductor wire. A semiconductor shell layer made of a second semiconductor material different from the first semiconductor material is formed around the semiconductor wire.

Abstract: A method for manufacturing a semiconductor device includes forming a source region, a drain region, and a gate dielectric layer and a gate electrode covering a channel region between the source region and the drain region, forming an insulating layer over the source region, the drain region, and the gate electrode, forming first to third vias penetrating the insulating layer and exposing portions of the source region, the drain region, and the gate electrode, respectively, forming a source contact in the first via to electrically connect to the source region, forming a drain contact in the second via to electrically connect to the drain region, and forming a gate contact in the third via to electrically connect to the gate electrode. One or more of the first to third vias is formed by ion bombarding by a focused ion beam and followed by a thermal annealing process.

Abstract: Various transistors, such as horizontal gate-all-around transistors, and methods of fabricating such are disclosed herein. An exemplary transistor includes a first nanowire and a second nanowire that include a first semiconductor material, a gate that wraps a channel region of the first nanowire and the second nanowire, and source/drain feature that wraps source/drain regions of the first nanowire and the second nanowire. The source/drain feature includes a second semiconductor material that is configured differently than the first semiconductor material. In some implementations, the transistor further includes a fin-like semiconductor layer disposed over a substrate. The first nanowire and the second nanowire are disposed over the fin-like semiconductor layer, such that the first nanowire, the second nanowire, and the fin-like semiconductor layer extend substantially parallel to one another along the same length-wise direction.

Abstract: A display device includes a circuit substrate and a light-emitting diode. Two electrodes of the light-emitting diode are connected to two pads of the circuit substrate. Each electrode of the light-emitting diode includes a first conductive layer, a barrier layer, and a metal layer. The first conductive layer is connected to a semiconductor stack layer of the light-emitting diode. The barrier layer is electrically connected to the semiconductor stack layer of the light-emitting diode through the first conductive layer. The adhesion of the material selected for the first conductive layer to the semiconductor stack layer is greater than the adhesion of the material selected for the barrier layer to the semiconductor stack layer. The metal layer electrically connects the barrier layer to the corresponding one of the pads. The melting point of the metal layer is lower than 260 degrees Celsius.

Abstract: An image capturing and depth alignment method includes radar scanning step, image capturing step, translation and synchronization step, alignment step, client detection step, client positioning step, scene map construction step, view image transmitting step, view image processing step, virtual object placement step. through translating, synchronizing, and aligning the radar scanning step's 3D point cloud map and the image capturing step's planar image of the scene, the back-end server therefore obtains surveillance information with both image and depth. Then, through positioning, multiply superimposing, image rotation and matching, speed comparison, uniformization of coordinate systems, and display through the smart glasses, a wearer of the smart glasses may be positioned and tracked in the scene. The wearer may also be instructed to reach a specific target or place of a specific object.

Abstract: A fabrication method of a display device includes the following steps: providing a light-emitting diode (LED) display device including an circuit substrate, first LEDs, and a second LED; detecting the LED display device, wherein the second LED cannot emit light normally; removing the second LED from the circuit substrate; providing a LED substrate; transferring a third LED of the LED substrate to a first transferring substrate; transferring the third LED on the first transferring substrate to a second transferring substrate; and electrically connecting the third LED on the second transposed substrate to the circuit substrate.

Abstract: A moiré pattern imaging device includes a light-transmissive film and a light-shielding film. The light-transmissive film includes a plurality of imaging units and a light-incident surface and a light-emergent surface opposite to each other. The plurality of imaging units are disposed on the light-incident surface, the light-emergent surface, or a combination thereof and are arranged in two dimensions to form an imaging unit array. The light-shielding film includes a plurality of light-transmissive regions. The light-transmissive regions are arranged in two dimensions to form a light-transmissive array, and the light-shielding film is overlaid on the light-incident surface or the light-emergent surface. The light-transmissive array corresponds to the imaging unit array. The imaging unit array and the light-transmissive array together form a moiré pattern effect to generate an image magnification effect.

Abstract: A holographic image film, and a holographic image recording method and reconstruction method are provided. The holographic image recording method includes a preparation step, an irradiation step and a recording step. The preparation step includes stacking a holographic negative film on a transparent substrate. The irradiation step includes emitting object light and reference light. The reference light is emitted into the transparent substrate and undergoes multiple times of total reflections in a thickness of the transparent substrate to form total internal reflected light. The recording step includes generating a holographic image interference line by a mutual interference between the total internal reflected light and the object light, and recording the holographic image interference line on the holographic negative film in a photosensitive manner.

Abstract: A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.

Abstract: Method and devices for creating a sedentary virtual-reality system are provided. A user interface is provided that allows for the intuitive navigation of the sedentary virtual-reality system based on the position of the users head. The sedentary virtual-reality system can render a desktop computing environment. The user can switch the virtual-reality system into an augmented reality viewing mode or a real-world viewing mode that allow the user to control and manipulate the rendered sedentary environment. The modes can also change to allow the user greater situational awareness and a longer duration of use.

Abstract: A thin proximity sensing device includes a transparent plate and a light sensor. The transparent plate includes a first surface and a second surface. The first surface is provided with a light source and a light entering area. The light source is arranged on the first surface. The second surface is provided with a reflector. The light sensor includes a light receiving area. The light sensor is arranged on the transparent plate. The reflector is capable of correspondingly reflecting specific incident light. The specific incident light refers to light that enters the transparent plate through the light entering area on the first surface after the light emitted by the light source is reflected externally, and is incident to the reflector. After reflected by the reflector, the specific incident light is reflected one or more times within the thickness of the transparent plate and is transmitted to the light sensor.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first source/drain structure and a second source/drain structure over a semiconductor substrate. The method also includes forming a dielectric layer over the first source/drain structure and the second source/drain structure and forming a conductive contact on the first source/drain structure. The method further includes forming a first conductive via over the conductive contact, and the first conductive via is misaligned with the first source/drain structure. In addition, the method includes forming a second conductive via directly above the second source/drain structure, and the second conductive via is longer than the first conductive via.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a multilayer stack over the base. The semiconductor device structure includes a gate stack over the substrate and wrapping around the multilayer stack. The semiconductor device structure includes a dielectric layer over the base and covering a first sidewall of the multilayer stack. A first upper surface of the dielectric layer is lower than a second upper surface of the multilayer stack. The semiconductor device structure includes a stressor over a second sidewall of the multilayer stack. The first sidewall is opposite to the second sidewall.

Abstract: A device includes an active region, a gate structure, an epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The epitaxial structure is above the active region and adjacent the gate structure. The epitaxial layer is above the epitaxial structure. The metal alloy layer is above the epitaxial layer. The contact is above the metal alloy layer. The contact etch stop layer lines sidewalls of the epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.