Patents by Inventor Hsiung Lin

Hsiung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11437385
    Abstract: A static random access memory (SRAM) cell includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The SRAM cell further includes n-type source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S/D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S/D contacts physically contacting each of the p-type S/D epitaxial features and the second portion of each of the first and the second hybrid fins.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Wang, Yi-Hsun Chiu, Yi-Hsiung Lin, Shang-Wen Chang
  • Publication number: 20220276939
    Abstract: A control method for error handling in a controller, storage medium therefor, controller, and storage device. The controller for use in a first device is capable of linking to a second device according to an interconnection protocol. The control method includes the following steps: handling a first error information by transmitting a negative acknowledgement control (NAC) message to the second device according to the interconnection protocol through the controller, wherein the first error information indicates a first error occurring while the controller performs data reception according to a protocol layer of the interconnection protocol; and setting error handling status data to indicate that error handling is asserted for the first error information so that the controller does not handle sequence number errors occurring after the first error until the error handling status data is set to indicate that the error handling is de-asserted.
    Type: Application
    Filed: December 28, 2021
    Publication date: September 1, 2022
    Applicant: SK hynix Inc.
    Inventors: WEN JYH LIN, YUN CHIH HUANG, FU HSIUNG LIN
  • Patent number: 11430891
    Abstract: Methods for manufacturing a semiconductor structure is provided. The method for manufacturing the semiconductor structure includes forming nanowire structures over a substrate and forming a gate structure across nanowire structures. The method for manufacturing the semiconductor structure also includes forming a source/drain structure adjacent to the gate structure and forming a Si layer over the source/drain structure. The method for manufacturing the semiconductor structure also includes forming a SiGe layer over the Si layer and oxidizing the SiGe layer to form an oxide layer. The method for manufacturing the semiconductor structure also includes forming a contact through the Si layer over the source/drain structure.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Han Wang, Pei-Hsun Wang, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20220254766
    Abstract: A display apparatus, including a circuit substrate, a driving unit and a light-emitting unit is provided. The driving unit is disposed on the circuit substrate. The light-emitting unit is disposed on the circuit substrate. A thickness of the driving unit is substantially the same as a thickness of the light-emitting unit.
    Type: Application
    Filed: July 16, 2021
    Publication date: August 11, 2022
    Applicant: Au Optronics Corporation
    Inventors: Yang-En Wu, Shih-Hsiung Lin
  • Patent number: 11404320
    Abstract: A fin field effect transistor device structure includes a first fin structure formed on a substrate. The fin field effect transistor device structure also includes a spacer layer surrounding the first fin structure. The fin field effect transistor device structure further includes a power rail formed over the substrate besides a bottom portion of the first fin structure. The fin field effect transistor device structure further includes a first contact structure formed over the first fin structure and in contact with a portion of the power rail.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Wen Chang, Yi-Hsiung Lin, Yi-Hsun Chiu
  • Publication number: 20220238341
    Abstract: A semiconductor structure includes a semiconductor fin extending from a substrate, a source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the S/D feature, where the silicide layer extends along a sidewall of the S/D feature, and an etch-stop layer (ESL) disposed along a sidewall of the silicide layer.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Inventors: Chun-Hsiung Lin, Shih-Cheng Chen, Chih-Hao Wang, Jung-Hung Chang, Jui-Chien Huang
  • Patent number: 11395078
    Abstract: Method and devices for testing a headphone with increased sensation are provided. The headphone can filter and amplify low frequency audio signals, which are then sent to a haptic device in the headphone. The haptic device can cause bass sensations at the top of the skull and at both ear cups. The testing system can evaluate the haptic and acoustic sensations produced by the headphone to evaluate if they have been properly assembled and calibrate the headphones if necessary.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: July 19, 2022
    Assignee: ALPINE ELECTRONICS OF SILICON VALLEY, INC.
    Inventors: Rocky Chau-Hsiung Lin, Thomas Yamasaki
  • Patent number: 11393815
    Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang, Ching-Wei Tsai, Yu-Xuan Huang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11380768
    Abstract: A device includes an active region, a gate structure, an epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The epitaxial structure is above the active region and adjacent the gate structure. The epitaxial layer is above the epitaxial structure. The metal alloy layer is above the epitaxial layer. The contact is above the metal alloy layer. The contact etch stop layer lines sidewalls of the epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20220208983
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Application
    Filed: March 14, 2022
    Publication date: June 30, 2022
    Inventors: Carlos H. Diaz, Chung-Wei Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Patent number: 11374108
    Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a first gate spacer, and an epitaxy structure. The substrate has a semiconductor fin. The isolation structure is over the substrate and laterally surrounds the semiconductor fin. The first gate structure is over the substrate and crosses the semiconductor fin. The first gate spacer extends along a sidewall of the first gate structure, in which the first gate spacer has a stepped sidewall distal to the first gate structure. The epitaxy structure is over the semiconductor fin, in which the epitaxy structure is in contact with the stepped sidewall of the first gate spacer.
    Type: Grant
    Filed: August 8, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Lun Chen, Bau-Ming Wang, Chun-Hsiung Lin
  • Patent number: 11373434
    Abstract: A fingerprint-recognition function in a backlit display device includes a cover plate, a display panel, a backlight module, and a fingerprint recognition module. The cover plate has an operating surface defining a touchable fingerprint identification area. The backlight module emits light for the display panel to display images and, as a first detection light, backlighting incident on the fingerprint identification area reflected by a fingerprint is taken and recognized by the recognition module. Along a thickness direction of the display device, a projection of the fingerprint identification module on the cover plate at least partially overlaps with the fingerprint identification area, and supplementary side-mounted sources emitting non-visible light enhance the accuracy of detection of the recognition module.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: June 28, 2022
    Assignee: JADARD TECHNOLOGY INC.
    Inventors: Hon-Yuan Leo, Jung-Tse Lee, Sheng-Hsiung Lin, Qing-Shan Yan
  • Publication number: 20220190137
    Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 16, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Han Wang, Ding-Kang Shih, Chun-Hsiung Lin, Teng-Chun Tsai, Zhi-Chang Lin, Akira Mineji, Yao-Sheng Huang
  • Patent number: 11355603
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hao Wu, Chia-Hao Chang, Chih-Hao Wang, Jia-Chuan You, Yi-Hsiung Lin, Zhi-Chang Lin, Chia-Hao Kuo, Ke-Jing Yu
  • Patent number: 11348836
    Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a fin protruding from a substrate and forming an isolation structure surrounding the fin. The method also includes epitaxially growing channel fins on sidewalls of the fin over the isolation structure and etching the fin to form a space between the channel fins. The method further includes forming a gate structure to fill the space between the channel fins.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Hsun Wang, Chun-Hsiung Lin, Chih-Hao Wang, Chih-Chao Chou
  • Publication number: 20220155181
    Abstract: A system is provided for estimating a tread depth of a tire supporting a vehicle. The tire includes a pair of sidewalls extending to a tread. The system includes a sensor unit, which includes a time of flight sensor. The sensor includes an emitter that emits a first pulse to an outer surface of the tread and a lens that captures the reflected first pulse. A processor measures a time from emission to capture of the first pulse, and calculates a tread surface distance from the time. The emitter emits a second pulse to a base of a tread groove and the lens captures the reflected second pulse. The processor measures a time from emission to capture of the second pulse, and calculates a reference distance from the time. The processor determines a depth of the tread from a difference between the tread surface distance and the reference distance.
    Type: Application
    Filed: November 17, 2020
    Publication date: May 19, 2022
    Inventor: Cheng-Hsiung Lin
  • Publication number: 20220130757
    Abstract: A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Inventors: Shang-Wen CHANG, Yi-Hsiung LIN
  • Patent number: 11309187
    Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the epitaxial S/D feature, the silicide layer is disposed on sidewalls of the epitaxial S/D feature, a dielectric layer disposed over sidewalls of the silicide layer, and an S/D contact disposed over the epitaxial S/D feature in an interlayer dielectric (ILD) layer.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Lin, Shih-Cheng Chen, Chih-Hao Wang, Jung-Hung Chang, Jui-Chien Huang
  • Patent number: 11285764
    Abstract: A control valve suitable for use with a tire and pump assembly is described that controls the flow of air from the pump into the tire. The control valve includes an optional bi-directional feature. The pathways alternatively operate to deliver ambient non-pressurized air to the air pumping tube in response to directional tire rotation against a ground surface.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: March 29, 2022
    Assignee: The Goodyear Tire & Rubber Company
    Inventors: Cheng-Hsiung Lin, Robin Lamgaday, Christos Tsionidis, Frank Herrigel, Marcus Boertje
  • Patent number: 11273801
    Abstract: A control system for an air maintenance tire system is provided. The control system includes a sensor unit that in turn includes a pressure sensor for measuring a pressure in the tire cavity and an antenna for transmitting pressure data. A processor receives the pressure data and includes a memory for storing a predetermined low-pressure threshold. Actuation means that are in communication with the processor and actuate and de-actuate operation of the air maintenance tire system. A first signal is transmitted from the processor to the actuation means to actuate operation of the air maintenance tire system when the measured pressure in the tire cavity is below the threshold. A second signal is transmitted from the processor to the actuation means to de-actuate operation of the air maintenance tire system when the measured pressure in the tire cavity is at or above the threshold.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 15, 2022
    Assignee: The Goodyear Tire & Rubber Company
    Inventors: Cheng-Hsiung Lin, James Andrews Euchner