Patents by Inventor Hsu-Yu Chang
Hsu-Yu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967615Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.Type: GrantFiled: December 23, 2015Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Hsu-Yu Chang, Neville L. Dias, Walid M. Hafez, Chia-Hong Jan, Roman W. Olac-Vaw, Chen-Guan Lee
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Publication number: 20240088253Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Inventors: Tanuj TRIVEDI, Rahul RAMASWAMY, Jeong Dong KIM, Babak FALLAHAZAD, Hsu-Yu CHANG, Ting CHANG, Nidhi NIDHI, Walid M. HAFEZ
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Patent number: 11862703Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.Type: GrantFiled: July 21, 2022Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Babak Fallahazad, Hsu-Yu Chang, Ting Chang, Nidhi Nidhi, Walid M. Hafez
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Publication number: 20230420501Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Inventors: Rahul RAMASWAMY, Walid M. HAFEZ, Tanuj TRIVEDI, Jeong Dong KIM, Ting CHANG, Babak FALLAHAZAD, Hsu-Yu CHANG, Nidhi NIDHI
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Patent number: 11791380Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.Type: GrantFiled: December 13, 2019Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Rahul Ramaswamy, Walid M. Hafez, Tanuj Trivedi, Jeong Dong Kim, Ting Chang, Babak Fallahazad, Hsu-Yu Chang, Nidhi Nidhi
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Patent number: 11581404Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.Type: GrantFiled: May 5, 2021Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Tanuj Trivedi, Jeong Dong Kim, Walid M. Hafez, Hsu-Yu Chang, Rahul Ramaswamy, Ting Chang, Babak Fallahazad
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Patent number: 11563000Abstract: Gate endcap architectures having relatively short vertical stack, and methods of fabricating gate endcap architectures having relatively short vertical stack, are described. In an example, an integrated circuit structure includes a first semiconductor fin along a first direction. A second semiconductor fin is along the first direction. A trench isolation material is between the first semiconductor fin and the second semiconductor fin. The trench isolation material has an uppermost surface below a top of the first and second semiconductor fins. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin and is along the first direction. The gate endcap isolation structure is on the uppermost surface of the trench isolation material.Type: GrantFiled: March 25, 2020Date of Patent: January 24, 2023Assignee: Intel CorporationInventors: Sairam Subramanian, Walid M. Hafez, Hsu-Yu Chang, Chia-Hong Jan
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Publication number: 20220359697Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Inventors: Tanuj TRIVEDI, Rahul RAMASWAMY, Jeong Dong KIM, Babak FALLAHAZAD, Hsu-Yu CHANG, Ting CHANG, Nidhi NIDHI, Walid M. HAFEZ
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Patent number: 11437483Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.Type: GrantFiled: March 5, 2020Date of Patent: September 6, 2022Assignee: Intel CorporationInventors: Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Babak Fallahazad, Hsu-Yu Chang, Ting Chang, Nidhi Nidhi, Walid M. Hafez
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Publication number: 20220093588Abstract: Adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, and methods of fabricating adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. One or more gate stacks is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between adjacent ones of the first epitaxial source or drain structures and between adjacent ones of the second epitaxial source or drain structures.Type: ApplicationFiled: September 18, 2020Publication date: March 24, 2022Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ, Hsu-Yu CHANG, Chia-Hong JAN, Tanuj TRIVEDI
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Publication number: 20210305243Abstract: Gate endcap architectures having relatively short vertical stack, and methods of fabricating gate endcap architectures having relatively short vertical stack, are described. In an example, an integrated circuit structure includes a first semiconductor fin along a first direction. A second semiconductor fin is along the first direction. A trench isolation material is between the first semiconductor fin and the second semiconductor fin. The trench isolation material has an uppermost surface below a top of the first and second semiconductor fins. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin and is along the first direction. The gate endcap isolation structure is on the uppermost surface of the trench isolation material.Type: ApplicationFiled: March 25, 2020Publication date: September 30, 2021Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ, Hsu-Yu CHANG, Chia-Hong JAN
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Patent number: 11121040Abstract: An apparatus comprising at least one transistor in a first area of a substrate and at least one transistor in a second area, a work function material on a channel region of each of the at least one transistor, wherein an amount of work function material in the first area is different than an amount of work function material in the second area. A method comprising depositing a work function material and a masking material on at least one transistor body in a first area and at least one in a second area; removing less than an entire portion of the masking material so that the portion of the work function material that is exposed in the first area is different than that exposed in the second area; removing the exposed work function material; and forming a gate electrode on each of the at least one transistor bodies.Type: GrantFiled: September 30, 2016Date of Patent: September 14, 2021Assignee: Intel CorporationInventors: Chen-Guan Lee, Everett S. Cassidy-Comfort, Joodong Park, Walid M. Hafez, Chia-Hong Jan, Rahul Ramaswamy, Neville L. Dias, Hsu-Yu Chang
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Publication number: 20210280683Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.Type: ApplicationFiled: March 5, 2020Publication date: September 9, 2021Inventors: Tanuj TRIVEDI, Rahul RAMASWAMY, Jeong Dong KIM, Babak FALLAHAZAD, Hsu-Yu CHANG, Ting CHANG, Nidhi NIDHI, Walid M. HAFEZ
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Publication number: 20210257452Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.Type: ApplicationFiled: February 19, 2020Publication date: August 19, 2021Inventors: Tanuj TRIVEDI, Jeong Dong KIM, Walid M. HAFEZ, Hsu-Yu CHANG, Rahul RAMASWAMY, Ting CHANG, Babak FALLAHAZAD
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Publication number: 20210257453Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.Type: ApplicationFiled: May 5, 2021Publication date: August 19, 2021Inventors: Tanuj TRIVEDI, Jeong Dong KIM, Walid M. HAFEZ, Hsu-Yu CHANG, Rahul RAMASWAMY, Ting CHANG, Babak FALLAHAZAD
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Patent number: 11094782Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.Type: GrantFiled: February 19, 2020Date of Patent: August 17, 2021Assignee: Intel CorporationInventors: Tanuj Trivedi, Jeong Dong Kim, Walid M. Hafez, Hsu-Yu Chang, Rahul Ramaswamy, Ting Chang, Babak Fallahazad
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Patent number: 11075286Abstract: A transistor including a source and a drain each formed in a substrate; a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewalls defining a width dimension of the channel and wherein the opposing sidewalls extend a distance below a surface of the substrate; and a gate electrode on the channel. A method of forming a transistor including forming a source and a drain in an area of a substrate; forming a source contact on the source and a drain contact on the drain; after forming the source contact and the drain contact, forming a channel in the substrate in an area between the source and drain, the channel including a body having opposing sidewalls separated by a length dimension; and forming a gate contact on the channel.Type: GrantFiled: December 12, 2016Date of Patent: July 27, 2021Assignee: Intel CorporationInventors: Chia-Hong Jan, Walid M. Hafez, Neville L. Dias, Rahul Ramaswamy, Hsu-Yu Chang, Roman W. Olac-Vaw, Chen-Guan Lee
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Publication number: 20210193844Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a source, a drain, and a semiconductor channel between the source and the drain. In an embodiment, the semiconductor channel has a non-uniform strain through a thickness of the semiconductor channel. In an embodiment, the semiconductor device further comprises a gate stack around the semiconductor channel.Type: ApplicationFiled: December 23, 2019Publication date: June 24, 2021Inventors: Rahul RAMASWAMY, Hsu-Yu CHANG, Babak FALLAHAZAD, Hsiao-Yuan WANG, Ting CHANG, Tanuj TRIVEDI, Jeong Dong KIM, Nidhi NIDHI, Walid M. HAFEZ
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Publication number: 20210184032Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a substrate, a source region over the substrate, a drain region over the substrate, and a semiconductor body extending from the source region to the drain region. In an embodiment, the semiconductor body has a first region with a first conductivity type and a second region with a second conductivity type. In an embodiment, the semiconductor device further comprises a gate structure over the first region of the semiconductor body, where the gate structure is closer to the source region than the drain region.Type: ApplicationFiled: December 13, 2019Publication date: June 17, 2021Inventors: Nidhi NIDHI, Rahul RAMASWAMY, Walid M. HAFEZ, Hsu-Yu CHANG, Ting CHANG, Babak FALLAHAZAD, Tanuj TRIVEDI, Jeong Dong KIM
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Publication number: 20210184045Abstract: Embodiments disclosed herein include nanoribbon and nanowire semiconductor devices. In an embodiment, the semiconductor device comprises a nanowire disposed above a substrate. In an embodiment, the nanowire has a first dopant concentration, and the nanowire comprises a pair of tip regions on opposite ends of the nanowire. In an embodiment, the tip regions comprise a second dopant concentration that is greater than the first dopant concentration. In an embodiment, the semiconductor device further comprises a gate structure over the nanowire. In an embodiment, the gate structure is wrapped around the nanowire, and the gate structure defines a channel region of the device. In an embodiment, a pair of source/drain regions are on opposite sides of the gate structure, and both source/drain regions contact the nanowire.Type: ApplicationFiled: December 13, 2019Publication date: June 17, 2021Inventors: Rahul RAMASWAMY, Walid M. HAFEZ, Nidhi NIDHI, Ting CHANG, Hsu-Yu CHANG, Tanuj TRIVEDI, Jeong Dong KIM, Babak FALLAHAZAD