Patents by Inventor Hsuan CHEN

Hsuan CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12367569
    Abstract: A method includes forming a package component, the package component comprising an integrated circuit die, attaching the package component to a package substrate; placing a heat spreader over the package component and the package substrate to form an integrated circuit package, wherein a height of the integrated circuit package is in a range from 2.5 mm to 6 mm, and performing a first automatic optical inspection (AOI) process on the integrated circuit package using an AOI apparatus to determine if the orientation and alignment of the heat spreader with regards to the package substrate is within specification, wherein the AOI apparatus comprises a lens that has a maximum depth of field that is greater than the height of the integrated circuit package, and wherein during the first AOI process the depth of field encompasses an entirety of the height of the integrated circuit package.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: July 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Hsuan Chen, Ying-Hao Wang, Chien-Lung Chen, Chien-Chi Tzeng, Hu-Wei Lin
  • Publication number: 20250234594
    Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor device structure. The method includes forming a fin structure over a substrate, forming an insulating material adjacent the fin structure, depositing a gate dielectric layer over the fin structure and the insulating material, depositing a gate electrode layer on the gate dielectric layer, forming an opening through the gate electrode layer and the gate dielectric layer into the insulating material, then performing an etch process that etches the gate dielectric layer at a faster rate than the gate electrode layer, and filling the opening with a dielectric material.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 17, 2025
    Inventors: Chao-Hsuan CHEN, I-Wei YANG, Shu-Yuan KU, Ryan Chia-Jen CHEN
  • Patent number: 12354910
    Abstract: A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.
    Type: Grant
    Filed: November 13, 2023
    Date of Patent: July 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huei-Wen Hsieh, Kai-Shiang Kuo, Cheng-Hui Weng, Chun-Sheng Chen, Wen-Hsuan Chen
  • Patent number: 12339632
    Abstract: A training method of a semiconductor process prediction model, a semiconductor process prediction device, and a semiconductor process prediction method are provided. The training method of the semiconductor process prediction model includes the following steps. The semiconductor process was performed on several samples. A plurality of process data of the samples are obtained. A plurality of electrical measurement data of the samples are obtained. Some of the samples having physical defects are filtered out according to the process data. The semiconductor process prediction model is trained according to the process data and the electrical measurement data of the filtered samples.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: June 24, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wei Chen, Ching-Pei Lin, Chung-Yi Chiu, Te-Hsuan Chen, Ming-Wei Chen, Hsiao-Ying Yang
  • Publication number: 20250192433
    Abstract: An electronic device includes a metal housing and an antenna structure. The metal housing includes a first housing and a second housing. The antenna structure is disposed between the first housing and the second housing. The antenna structure includes a carrier, a radiating element, a grounding metal member, a first grounding extension structure, and a reactive element. A first metal portion of the grounding metal member is electrically connected to the first housing, and a second metal portion of the grounding metal member is electrically connected to the second housing. The first grounding extension structure is connected to the first metal portion and the second metal portion. The reactive element is electrically connected between the radiating element and the second metal portion.
    Type: Application
    Filed: August 27, 2024
    Publication date: June 12, 2025
    Inventors: SHIH-CHIANG WEI, Ying-Hsuan Chen, HSIEH-CHIH LIN
  • Patent number: 12327936
    Abstract: A light-transmitting antenna includes a substrate, a first conductive pattern, and a second conductive pattern. The first conductive pattern has a first feeder unit, a first radiation unit, a second radiation unit, and a first connection unit. The first feeder unit and the first connection unit are connected to two sides of the first radiation unit. The first connection unit connects the first radiation unit and the second radiation unit. The second conductive pattern has a second feeder unit, a third radiation unit, a fourth radiation unit, and a second connection unit. The second feeder unit and the second connection unit are connected to two sides of the third radiation unit. The second connection unit connects the third radiation unit and the fourth radiation unit. An orthogonal projection of the second feeder unit on a first surface of the substrate at least partially overlaps the first feeder unit.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: June 10, 2025
    Assignee: Industrial Technology Research Institute
    Inventors: Meng-Hsuan Chen, Cheng-Hua Tsai, Mei-Ju Lee, Ruo-Lan Chang, Wei-Chung Chen
  • Publication number: 20250185228
    Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.
    Type: Application
    Filed: February 3, 2025
    Publication date: June 5, 2025
    Inventors: Chia-Hao PAO, Chih-Chuan YANG, Shih-Hao LIN, Chih-Hsuan CHEN, Chao-Yuan CHANG, Feng-Ming CHANG, Kian-Long LIM, Lien-Jung HUNG, Ping-Wei WANG
  • Patent number: 12315738
    Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.
    Type: Grant
    Filed: June 13, 2024
    Date of Patent: May 27, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hao Lin, Jui-Lin Chen, Hsin-Wen Su, Kian-Long Lim, Bwo-Ning Chen, Chih-Hsuan Chen
  • Publication number: 20250166220
    Abstract: A head wearable display system comprising a target object detection module receiving multiple image pixels of a first portion and a second portion of a target object, and the corresponding depths; a first light emitter emitting multiple first-eye light signals to display a first-eye virtual image of the first portion and the second portion of the target object for a viewer; a first light direction modifier for respectively varying a light direction of each of the multiple first-eye light signals emitted from the first light emitter; a first collimator; a first combiner, for redirecting and converging the multiple first-eye light signals towards a first eye of the viewer. The first-eye virtual image of the first portion of the target object in a first field of view has a greater number of the multiple first-eye light signals per degree than that of the first-eye virtual image of the second portion of the target object in a second field of view.
    Type: Application
    Filed: January 21, 2025
    Publication date: May 22, 2025
    Applicant: Oomii Inc.
    Inventors: Feng-Chun YEH, Guo-Hsuan CHEN, Jiunn-Yiing LAI, Yin CHANG, Po-Ya HSU
  • Publication number: 20250166695
    Abstract: Some embodiments relate to a memory cell, including: a write transistor on a substrate and comprising a first gate terminal, a first source/drain region, and a second source/drain region coupled to a storage node; a first read transistor on the substrate and comprising a second gate terminal coupled to the storage node and a gate dielectric with a first capacitance; and a capacitor spaced from the first read transistor and the write transistor and further separated from the substrate by the first read transistor and the write transistor, wherein the capacitor is coupled to the storage node and has a second capacitance that is over twice the first capacitance.
    Type: Application
    Filed: April 23, 2024
    Publication date: May 22, 2025
    Inventors: Wei Ting Hsieh, Kuen-Yi Chen, Yu-Wei Ting, Yi Ching Ong, Kuo-Ching Huang, Yi-Hsuan Chen
  • Patent number: 12302596
    Abstract: A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsuan Chen, Ming-Chia Tai, Yu-Hsien Lin, Shun-Hui Yang, Ryan Chia-Jen Chen
  • Patent number: 12302628
    Abstract: The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Ching Ong, Kuen-Yi Chen, Yi-Hsuan Chen, Kuo-Ching Huang, Harry-Hak-Lay Chuang
  • Publication number: 20250147223
    Abstract: A backlight module has a first side viewing angle luminance LAS1 and a first normal viewing angle luminance LAN1 in the side viewing mode, wherein LAS1/LAN1>50%. The backlight module has a second side viewing angle luminance LAS2 and a second normal viewing angle luminance LAN2 in the narrow viewing mode, wherein LAS2/LAN2<0.5%. The first side angle and the second side angle occur in a slanting direction. The first normal view and the second normal view occur in a normal direction. When executing a side viewing execution step, an upper backlight unit and a lower backlight unit are activated to form the side viewing mode. When executing a narrow viewing execution step, the upper backlight unit is turned off and the lower backlight unit is activated to form the narrow viewing mode. The invention also provides a display device including the backlight module.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 8, 2025
    Applicant: Radiant Opto-Electronics Corporation
    Inventors: Chun-Hau LAI, Wei-Hsuan CHEN, Chun-Yi WU
  • Patent number: 12294030
    Abstract: A semiconductor structure includes a first pair of source/drain features (S/D), a first stack of channel layers connected to the first pair of S/D, a second pair of S/D, and a second stack of channel layers connected to the second pair of S/D. The first pair of S/D each include a first epitaxial layer having a first dopant, a second epitaxial layer having a second dopant and disposed over the first epitaxial layer and connected to the first stack of channel layers, and a third epitaxial layer having a third dopant and disposed over the second epitaxial layer. The second pair of S/D each include a fourth epitaxial layer having a fourth dopant and connected to the second stack of channel layers, and a fifth epitaxial layer having a fifth dopant and disposed over the fourth epitaxial layer. The first dopant through the fourth dopant are of different species.
    Type: Grant
    Filed: May 24, 2024
    Date of Patent: May 6, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su, Chia-Wei Chen
  • Publication number: 20250142836
    Abstract: A neural network circuit includes an input neuron layer comprises a plurality of first neurons. A hidden neuron layer includes a plurality of second neurons, wherein each of the second neurons comprises a probabilistic bit having a time-varying resistance. The probabilistic bit is a magnetic tunnel junction structure comprises a pinned layer, a free layer, and a tunneling barrier layer between the pinned layer and the free layer. A weight matrix comprising a plurality of synapse units, each of the synapse units connecting one of the plurality of first neurons to a corresponding one of the plurality of first neurons.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 1, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Sheng CHEN, Kuen-Yi CHEN, Yi-Hsuan CHEN, Hsin Heng WANG, Yi Ching ONG, Kuo-Ching HUANG
  • Publication number: 20250139478
    Abstract: A control signal transmission device for a quantum computer is provided. The control signal transmission device includes a laser source, a digital-to-analog converter (DAC), an electro-optic modulation circuit, an optical fiber, an optic-electro demodulation circuit and a plurality of qubits. The laser source provides a light. The DAC provides a plurality of first control signals. The electro-optic modulation circuit integrates the corresponding first control signals into the light to generate an optical signal, and provides the optical signal to the optical fiber. The optic-electro demodulation circuit converts and splits the optical signal into a plurality of second control signals. The optic-electro demodulation circuit transmits the second control signals to the corresponding qubits. The qubits are controlled by the corresponding second control signals. An ambient temperature set by the optic-electro demodulation circuit and the qubits is much lower than a preset temperature value.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 1, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Che-Hao Li, Wei Chaun Yu, Po-Sheng Chang, Meng-Hsuan Chen
  • Publication number: 20250133694
    Abstract: A mounting assembly is provided for mounting a liquid cooling adaptor manifold to a server rack. The mounting assembly includes the liquid cooling adaptor, a mounting adaptor, and a mounting bracket. The liquid cooling adaptor provides a cooling liquid from a source via first connectors of a first type to a device via second connectors of a second type. The mounting adaptor is affixed to the liquid cooling adaptor manifold and to the mounting bracket. The mounting bracket is affixed to a side wall of a server rack.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 24, 2025
    Inventor: Yi-Hsuan Chen
  • Publication number: 20250130935
    Abstract: A device control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: establishing a connection between the memory storage device and a host system; performing a first communication with the host system based on the connection and a first connection interface standard; performing a data recovery operation between the memory storage device and the host system via the connection during a period of performing the first communication; and switching to perform a second communication with the host system based on the connection and a second connection interface standard in a case that the data recovery operation is successfully performed, wherein the first connection interface standard is different from the second connection interface standard.
    Type: Application
    Filed: November 28, 2023
    Publication date: April 24, 2025
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yuwei Kuo, Hung Yuan Tsai, Chun Ming Liu, Yu Hsuan Chen, Yun-You Lin
  • Publication number: 20250133761
    Abstract: A semiconductor structure includes a substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers are over the substrate and spaced apart from each other in a Z-direction. The source/drain features are over the substrate. The semiconductor layers are between the source/drain features. The metal oxide layers are on top surfaces and bottom surfaces of the semiconductor layers. The gate structure covers and is in contact with center portions of the metal oxide layers on top surfaces and bottom surfaces of the semiconductor layers.
    Type: Application
    Filed: December 30, 2024
    Publication date: April 24, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hao LIN, Chia-Hung CHOU, Chih-Hsuan CHEN, Ping-En CHENG, Hsin-Wen SU, Chien-Chih LIN, Szu-Chi YANG
  • Publication number: 20250123424
    Abstract: A light guide film comprises a base material layer, an upper ultraviolet adhesive layer, a lower ultraviolet adhesive layer, two optical adhesive layers and a light incident microstructure unit. The base material layer has a light incident surface. The upper ultraviolet adhesive layer is disposed above the base material layer. The lower ultraviolet adhesive layer is disposed below the base material layer. The two optical adhesive layers are disposed above the upper ultraviolet adhesive layer and below the lower ultraviolet adhesive layer, respectively. The light incident microstructure unit has a first microstructure region disposed on the light incident surface of the base material layer.
    Type: Application
    Filed: October 11, 2024
    Publication date: April 17, 2025
    Inventors: Wei-Hsuan CHEN, Yung-Hui TAI, Yuan-Chen CHUNG