Abstract: An actuating module includes a frame, a light-transmitting element, at least one actuator, and a light shielding member. The light-transmitting element is disposed on the frame. A part of at least one actuator is connected to the frame for driving the frame to vibrate. The light shielding member is configured to overlap at least a part of an incident surface, a light emitting surface or one of a combination thereof of the light-transmitting element for reflecting and/or absorbing a light beam. The actuating module may be configured in a projection device, and the light shielding member may prevent an ineffective light beam from entering a projection lens, so as to reduce the light leakage caused by the ineffective light beam entering the projection lens, thereby improving the display effect in an off state.

Abstract: A filter integrated circuit, including an acoustic wave filter chip and a matching circuit, is provided. The acoustic wave filter chip is covered upon a substrate. The matching circuit is disposed on the substrate to provide matching impedance to the acoustic wave filter chip. A first pad and a second pad of the matching circuit are respectively connected to a first signal terminal and a second signal terminal of the acoustic wave filter chip. First terminals of a first coil inductor and a second coil inductor of the matching circuit are respectively connected to the first pad and the second pad of the substrate. The first coil inductor is adjacent to the second coil inductor, so that mutual inductance and parasitic capacitance are formed, so that the matching circuit and the acoustic wave filter chip jointly generate a transmission zero point located in a triple fundamental frequency range.

Abstract: A first n-type transistor includes a first channel component, an undoped first gate dielectric layer disposed over the first channel component, and a first gate electrode disposed over the undoped first gate dielectric layer. A second n-type transistor includes a second channel component and a doped second gate dielectric layer disposed over the second channel component. The second gate dielectric layer is doped with a p-type dipole material. A second gate electrode is disposed over the second gate dielectric layer. At least one of the first n-type transistor or the second n-type transistor further includes an aluminum-free conductive layer. The aluminum-free conductive layer is disposed between the first gate dielectric layer and the first gate electrode or between the second gate dielectric layer and the second gate electrode.

Abstract: Disclosed are systems and methods for superimposing a virtual image on a real-time image. A system for superimposing a virtual image on a real-time image comprises a real-time image module and a virtual image module. The real-time image module comprises a magnification assembly to generate a real-time image of an object at a first location and a first depth, with a predetermined magnification. The virtual image module generates a virtual image by respectively projecting a right light signal to a viewer's right eye and a corresponding left light signal to a viewer's left eye. The right light signal and the corresponding left light signal are perceived by the viewer to display the virtual image at a second location and a second depth. The second depth is related to an angle between the right light signal and the corresponding left light signal projected to the viewer's eyes. The second depth may be approximately the same as the first depth.

Abstract: A method of predicting the efficacy of natural killer cells, including: generating a plurality of training data corresponding to a plurality of donors based on a characteristic factor and a corresponding killing result against the target cancer cells of a plurality of cultured natural killer cells from the donors; obtaining a trained neural network model by inputting the plurality of training data into a neural network model; inputting a to-be-tested input vector corresponding to at least one characteristic factor of a to-be-tested natural killer cell into the trained neural network model to obtain an outputted result vector of the trained neural network model, wherein the result vector indicates a predicted killing result corresponding to the target cancer cell after applying the to-be-tested natural killer cell; and determining a quality of the to-be-tested natural killer cell based on the predicted killing result.

Abstract: A semiconductor structure includes a first pair of source/drain features (S/D), a first stack of channel layers connected to the first pair of S/D, a second pair of S/D, and a second stack of channel layers connected to the second pair of S/D. The first pair of S/D each include a first epitaxial layer having a first dopant, a second epitaxial layer having a second dopant and disposed over the first epitaxial layer and connected to the first stack of channel layers, and a third epitaxial layer having a third dopant and disposed over the second epitaxial layer. The second pair of S/D each include a fourth epitaxial layer having a fourth dopant and connected to the second stack of channel layers, and a fifth epitaxial layer having a fifth dopant and disposed over the fourth epitaxial layer. The first dopant through the fourth dopant are of different species.

Abstract: There is provided a bottom cover for being covered on an optical system. The bottom cover is attached in front of the optical engine. The bottom cover has a bottom surface for facing a working surface when the optical system is moving on the working surface, a first opening for emission light of the optical engine to go through and a second opening for reflected light from the working surface to go through. The bottom cover is further formed with guiding protrusions protruded out from the bottom surface toward the working surface and surrounding at least the second opening to guide soft materials on the working surface to away from the second opening.

Abstract: Systems and methods for global positioning satellite (GPS)/global navigation satellite system (GNSS) based real time global asset tracking are described. In an embodiment provides a system for real time, fast, global asset tracking, the system includes: a server with a processor, a memory, and a network interface, wherein the memory includes a tracking application, where the tracking application directs the processor to: receive a message including specific data from a tag; determine a time search window based on the message received from the tag; perform an initial position search; perform calculations for position and time, utilizing the time search window, the initial position search and satellite ephemeris information; and display a position information of the tag.

Abstract: A method for evaluating data to be used to train an object recognition model is to be implemented by a computing device. The computing device stores a plurality of training datasets respectively related to a plurality of images, and each training dataset includes a plurality of entries of training data. The method includes steps of: obtaining, for each image, at least one target area and at least one target property that are related to the image based on the entries of training data; creating, for each image, a training material that includes the image, and the at least one target area and the at least one target property both related to the image; and obtaining at least three object recognition models based on the training materials that are created respectively for the images using at least one machine learning algorithm.

Abstract: There is provided an optical engine for a navigation device including a first light source, a second light source, a lens, a carrier member and an image sensor. The carrier member has a light holder, a lens holder, an accommodation space and a tilted wall. The first light source is arranged on the light holder of the carrier member, and reflected light associated with the first light source penetrates through the lens to propagate to the image sensor inside the accommodation space. Reflected light associated with the second light source penetrates through the tilted wall of the carrier member to propagate to the image sensor.

Abstract: The present application provides methods and systems to identify host cell protein (HCP) impurities in a sample containing high-abundance proteins. The HCP impurities can be enriched using interacting peptide ligands which have been attached to solid support. The HCP impurities can be eluted from the solid support using solution containing phase transfer surfactants. The isolated HCP impurities can be digested to generate components of the isolated HCP impurities which can subsequently be identified using a mass spectrometer.

Abstract: The present disclosure relates to a visual depth calibration system for accurately rendering visual depth perception of a virtual image in head wearable display, comprising a first distance measurement unit for determining a first distance between a first object and a viewer, and a second distance between a second object and the viewer; a first light direction modifier and a second light direction modifier for respectively and changing a direction of a first light signal and a second light signal emitted by a first emitter and a second emitter such that the first light signal and the second light signal are respectively emitted toward a first eye and a second eye with a first angle and a second angle that are altering relative a frontal plane of the viewer to render a binocular virtual image having variable depth perception for the viewer.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

Abstract: A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.

Abstract: An image capturing system lens assembly is disclosed, comprising seven lens elements, the seven lens elements being, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, and a seventh lens element. Each of the seven lens elements has an object-side surface facing the object side and an image-side surface facing the image side. An axial distance between the object-side surface of the first lens element and an image surface is TL, a focal length of the image capturing system lens assembly is f, and the following condition is satisfied: 6.00<TL/f<28.00.

Abstract: A device includes a first and a second stacks of channel layers each extending from a first height to a second height. A first dielectric feature on a first side of the first stack and between the first and the second stacks extends from a third height to a fourth height. A second dielectric feature on a second side of the first stack opposite to the first side extends from the third height to a fifth height. A gate electrode extends continuously across a top surface of the first and the second stacks and extends to a sixth height. The fifth height is above the sixth height, the sixth height is above the second height, the second height is above the fourth height, the fourth height is above the first height, and the first height is above the third height.

Abstract: A nano-twinned Cu—Ni alloy layer is provided, wherein more than 50% in volume of the nano-twinned Cu—Ni alloy layer comprises plural twinned grains, the plural twinned grains comprise plural columnar twinned grains, and a Ni content in the nano-twinned Cu—Ni alloy layer is in a range from 0.05 at % to 20 at %. In addition, a method for manufacturing the aforesaid nano-twinned Cu—Ni alloy layer is also provided.