Abstract: The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

Abstract: According to various embodiments described herein, a device includes a control circuit, a time-to-digital converter circuit coupled having a first output coupled to a first input of the control circuit, and a gating circuit having a first input coupled to a first signal, a second input coupled to a second signal, and an output coupled to a first input of the time-to-digital converter circuit, an output of the control circuit coupled to a second input of the time-to-digital converter circuit and to a third input of the gating circuit.

Abstract: An open-loop GPS antenna configured on an insulation object is provided. The open-loop GPS antenna includes a feed, a high frequency circuit, a low frequency circuit and a ground. The high frequency circuit includes a first end, connected to the feed, and a second end. The low frequency circuit includes a third end and a fourth end. The third end is disposed parallel to the second end so as to couple to the second end and generate a capacitance effect to transmit a signal. The fourth end is connected to the ground.

Abstract: A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a VCO input for receiving a control voltage and a VCO output, a feedback loop between the VCO input and the VCO output, and a start-up circuit having a start-up circuit input and a start-up circuit output. The start-up circuit output is coupled to the VCO input and the start-up circuit input is coupled to the VCO output. The start-up circuit provides a voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the start-up circuit.

Abstract: Among other things, one or more techniques or systems for delay path selection are provided. A digitally controlled oscillator comprises an arrangement of inverters, such as tri-state inverters, that are selectively utilized to provide a process, voltage, temperature (PVT) condition output used to generate a frequency output for the digitally controlled oscillator. Delay path interpolation is used to generate a relatively high resolution range of PVT condition outputs, which results in a reduction of frequency gain (KDOC) between PVT condition outputs for improved performance of the digitally controlled oscillator.

Abstract: Among other things, one or more techniques or systems for delay path selection are provided. A digitally controlled oscillator comprises an arrangement of inverters, such as tri-state inverters, that are selectively utilized to provide a process, voltage, temperature (PVT) condition output used to generate a frequency output for the digitally controlled oscillator. Delay path interpolation is used to generate a relatively high resolution range of PVT condition outputs, which results in a reduction of frequency gain (KDOC) between PVT condition outputs for improved performance of the digitally controlled oscillator.

Abstract: A printed circuit board (PCB) includes a substrate, a pad, a plurality of connecting wires and a plurality of separating portions. The pad arranged on at least one surface of the substrate. The plurality of connecting wires increase contact area of the pad and a copper foil around the pad to keep the current of the PCB steady when a lot of current flow through the PCB. The plurality of separating portions located on between the pad and the copper foil around the pad to divide the pad and the copper foil to avoid short-circuit when the copper foil is etched.

Abstract: A dynamic scaling processor device and processing method thereof, having a timing decoder, a multi-cycle controller, a correction flip-flop. The timing decoder is provided with a plurality of cycles therein, to receive a plurality of instructions, to select corresponding cycles as its predetermined cycles based on type of each instruction, and output the predetermined cycles and its corresponding instructions to the multi-cycle controller. The multi-cycle controller computes results of the instructions based on the predetermined cycles or a single cycle, and outputs them to the correction flip-flop. The error detection flip-flop utilizes a first clock signal and a stalled second clock signal, to sample a same result, and correct the results when outcomes of samplings are different.

Abstract: An open-loop GPS antenna configured on an insulation object is provided. The open-loop GPS antenna includes a feed, a high frequency circuit, a low frequency circuit and a ground. The high frequency circuit includes a first end, connected to the feed, and a second end. The low frequency circuit includes a third end and a fourth end. The third end is disposed parallel to the second end so as to couple to the second end and generate a capacitance effect to transmit a signal. The fourth end is connected to the ground.

Abstract: A digital controlled delay line (DCDL) includes a signal gated delay line generating a delayed signal, a phase selector, a controller, an input signal and an output signal. The phase selector includes logic gates to couple the delayed signal from the signal gated delay line to the output signal. Preventing signal propagation to unused cells and logic gates reduces power consumption. The number of logic gates in the phase selector the delayed signal passes through is log2 p, wherein p is the number of the signal gated delay cells in the signal gated delay line and p is a power of 2. The number of logic gates is (integer part of log2 p)+1, wherein p is the number of the signal gated delay cells and p is not a power of 2.

Abstract: A digital controlled delay line (DCDL) includes a signal gated delay line generating a delayed signal, a phase selector, a controller, an input signal and an output signal. The phase selector includes logic gates to couple the delayed signal from the signal gated delay line to the output signal. Preventing signal propagation to unused cells and logic gates reduces power consumption. The number of logic gates in the phase selector the delayed signal passes through is log2 p, wherein p is the number of the signal gated delay cells in the signal gated delay line and p is a power of 2. The number of logic gates is (integer part of log2 p)+1, wherein p is the number of the signal gated delay cells and p is not a power of 2.

Abstract: The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

Abstract: A phase locked loop (PLL) circuit includes a frequency multiplier and a fractional-N type PLL. The clock output of the frequency multiplier is electrically connected to the clock input of the fractional-N type PLL. The loop bandwidth of the frequency multiplier of the PLL is smaller than the loop bandwidth of the fractional-N type PLL of the PLL.

Abstract: A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison.

Abstract: A printed circuit board (PCB) includes a substrate, a pad, a plurality of connecting wires and a plurality of separating portions. The pad arranged on at least one surface of the substrate. The plurality of connecting wires increase contact area of the pad and a copper foil around the pad to keep the current of the PCB steady when a lot of current flow through the PCB. The plurality of separating portions located on between the pad and the copper foil around the pad to divide the pad and the copper foil to avoid short-circuit when the copper foil is etched.

Abstract: A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison.

Abstract: The present invention provides a carrier component. The carrier component includes a carrier core body including a dispersive object and a dualistic self-assembly material for encapsulating the dispersive object, wherein the dualistic self-assembly material has an electric charge; and a first shell layer having an electric charge opposite to the electric charge of the dualistic self-assembly material, and coating the carrier core body, and thus avoids inactivation of a medicine, eliminates medicine leakage and reduces medicine releasing. The present invention further provides a method for forming a carrier component.