Patents by Inventor HSUAN CHOU

HSUAN CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230190832
    Abstract: A strain of Lactobacillus paracasei for promoting hair growth, a hair product having same, and a use thereof are disclosed. The strain of Lactobacillus paracasei is Lactobacillus paracasei GMNL-653, which was deposited at the China Center for Type Culture Collection in Wuhan, China on Apr. 25, 2016 under an accession number CCTCC NO. M 2016226.
    Type: Application
    Filed: April 8, 2022
    Publication date: June 22, 2023
    Applicant: GENMONT BIOTECH INC.
    Inventors: Wan-hua Tsai, Chia-hsuan Chou, Tsuei yin Huang, Ying-ju Chiang, Ching-gong Lin
  • Patent number: 11672081
    Abstract: A manufacturing method of a metal structure is disclosed, which includes the following steps: forming a seed layer on a substrate; forming a patterned metal layer on the seed layer, wherein the patterned metal layer includes a metal member; forming a first patterned photoresist layer on the seed layer, wherein a thickness of the first patterned photoresist layer is less than a thickness of the patterned metal layer; and performing a first patterning process to the seed layer through the first patterned photoresist layer to form a patterned seed layer, wherein after the first patterning process, the metal member includes a first part and a second part, the first part is disposed between the patterned seed layer and the second part, and a width of the first part is greater than a width of the second part.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: June 6, 2023
    Assignee: InnoLux Corporation
    Inventors: Hsueh-Hsuan Chou, Yi-Hung Lin
  • Patent number: 11664793
    Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: May 30, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
  • Publication number: 20230139904
    Abstract: Disclosed herein is a method for promoting bone healing using Lactobacillus plantarum TWK10 (CGMCC No. 13008).
    Type: Application
    Filed: April 21, 2022
    Publication date: May 4, 2023
    Inventors: YU-TZU HUANG, HSUAN CHOU, JYUN-SIAN WU, CHIA-CHIA LEE, HAN-YIN HSU
  • Publication number: 20230027220
    Abstract: The present disclosure provides a package device and a manufacturing method thereof. The package device includes an electronic device, a conductive pad having a first bottom surface, and a redistribution layer disposed between the conductive pad and the electronic device. The redistribution layer has a second bottom surface, and the conductive pad is electrically connected to the electronic device through the redistribution layer. The first bottom surface is closer to the electronic device than the second bottom in a normal direction of the electronic device.
    Type: Application
    Filed: October 5, 2022
    Publication date: January 26, 2023
    Applicant: InnoLux Corporation
    Inventors: Hsueh-Hsuan Chou, Chia-Chieh Fan, Kuan-Jen Wang, Cheng-Chi Wang, Yi-Hung Lin, Li-Wei Sung
  • Patent number: 11555851
    Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: January 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 11555842
    Abstract: A system, a method and a built-in phase noise measurement apparatus are introduced. The built-in phase noise measurement apparatus includes a first DLL and a TDC, in which the first DLL circuit controls a delay of a first signal to generate a second signal based on a control code, tune the control code until a phase of the second signal is aligned to a phase of a reference clock signal, and record a value of the control code when the phase of the second signal is aligned to the phase of the reference clock signal. The DLL circuit controls the delay of the first signal based on the value of the control code after the phase of the second signal is aligned to the phase of the reference clock signal. The TDC determines the phase noise of the first signal based on the reference clock signal and the second signal.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Hsuan Chou, Chih-Hsien Chang, Ruey-Bin Sheen, Ya-Tin Chang
  • Patent number: 11541084
    Abstract: A composition having Lactobacillus Plantarum strain GMNL-662 for promoting bone regrowth is provided. The Lactobacillus Plantarum strain GMNL-662 has an ability to promote the expression of osteogenic genes, inhibit the expression of osteoclast related genes, and promote the expression of osteogenesis-related cytokine TGF-?, so that the bone loss is improved.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: January 3, 2023
    Assignee: .GENMONT BIOTECH INC
    Inventors: Yi-Hsing Chen, Wan-Hua Tsai, Chia-Hsuan Chou, Chi Chien Lin
  • Publication number: 20220349041
    Abstract: Disclosed are rare earth metal containing silicate coatings, coated articles (e.g., heaters and susceptors) or bodies of articles and methods of coating such articles with a rare earth metal containing silicate coating.
    Type: Application
    Filed: July 14, 2022
    Publication date: November 3, 2022
    Inventors: Xiao-Ming He, Cheng-Hsuan Chou, Jennifer Y. Sun
  • Patent number: 11488899
    Abstract: The present disclosure provides a package device including a conductive pad, a protecting block, and a redistribution layer. The protecting block is disposed on the conductive pad. The redistribution layer is disposed on the protecting block, and the conductive pad is electrically connected to the redistribution layer through the protecting block.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: November 1, 2022
    Assignee: InnoLux Corporation
    Inventors: Hsueh-Hsuan Chou, Chia-Chieh Fan, Kuan-Jen Wang, Cheng-Chi Wang, Yi-Hung Lin, Li-Wei Sung
  • Publication number: 20220294460
    Abstract: A counter signal counting at a frequency of a clock signal is generated. Among a plurality of different numeric ranges corresponding to a plurality of different thresholds, a threshold corresponding to a numeric range containing a frequency ratio is selected. In response to the counter signal reaching the selected threshold, a logic level of an output signal is switched.
    Type: Application
    Filed: May 31, 2022
    Publication date: September 15, 2022
    Inventors: Mao-Hsuan CHOU, Chih-Hsien CHANG, Ruey-Bin SHEEN
  • Publication number: 20220286141
    Abstract: A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
  • Publication number: 20220260634
    Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).
    Type: Application
    Filed: May 4, 2022
    Publication date: August 18, 2022
    Inventors: Mao-Hsuan CHOU, Ya-Tin CHANG, Ruey-Bin SHEEN, Chih-Hsien CHANG
  • Patent number: 11401599
    Abstract: Disclosed are rare earth metal containing silicate coatings, coated articles (e.g., heaters and susceptors) or bodies of articles and methods of coating such articles with a rare earth metal containing silicate coating.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: August 2, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Xiao-Ming He, Cheng-Hsuan Chou, Jennifer Y. Sun
  • Patent number: 11374584
    Abstract: A frequency divider circuit includes a counter configured to generate a counter signal responsive to a frequency of a clock signal and a frequency ratio, and a compensation circuit coupled to the counter, and configured to generate an output signal. The output signal has a frequency equal to the frequency of the clock signal divided by a frequency ratio, and a duty cycle lower than 50% and greater than 1/r, where r is the frequency ratio.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mao-Hsuan Chou, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 11356115
    Abstract: A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 11333708
    Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 11318176
    Abstract: The present invention relates to a topical composition of facilitating wound healing and reducing scars, which includes an inactivated culture of Lactobacillus species as an effective ingredient and can significantly facilitate wound healing as well as reducing scars, thereby can be applied to a method of facilitating wound healing and reducing scars.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 3, 2022
    Assignee: GenMont Biotech Incorporation
    Inventors: Yi-Hsing Chen, Wan-Hua Tsai, Wen-Wei Chang, Chia-Hsuan Chou
  • Publication number: 20220131536
    Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Inventors: Mao-Hsuan CHOU, Ya-Tin CHANG, Ruey-Bin SHEEN, Chih-Hsien CHANG
  • Publication number: 20220082602
    Abstract: A system, a method and a built-in phase noise measurement apparatus are introduced. The built-in phase noise measurement apparatus includes a first DLL and a TDC, in which the first DLL circuit controls a delay of a first signal to generate a second signal based on a control code, tune the control code until a phase of the second signal is aligned to a phase of a reference clock signal, and record a value of the control code when the phase of the second signal is aligned to the phase of the reference clock signal. The DLL circuit controls the delay of the first signal based on the value of the control code after the phase of the second signal is aligned to the phase of the reference clock signal. The TDC determines the phase noise of the first signal based on the reference clock signal and the second signal.
    Type: Application
    Filed: September 11, 2020
    Publication date: March 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Hsuan Chou, Chih-Hsien Chang, Ruey-Bin Sheen, Ya-Tin Chang