Abstract: A rectangular parallelepiped (RP) cell region includes: a 3D L-shape region, a dummy region and a resident region each of which includes transistor components, transistors of the resident region being free from comprising a function of the L-shape region; the dummy region and the resident region being in first notch formed by an arm and a stem of the L-shape region; first type transistors of the arm being stacked correspondingly over second type transistors of the first part of the stem; dummy transistor(s) of the dummy region being stacked over second type transistors of the second part of the stem; and first type transistors of the resident region being stacked over second type transistors of the third part of the stem.

Abstract: An electronic device includes a metal back cover and an antenna module. The metal back cover includes a slit. The antenna module is separated from the metal back cover and disposed far away from the slit. The antenna module includes an antenna radiator, a first ground radiator, and a connection radiator. The antenna radiator includes a first section, a second section, and a third section that are sequentially connected and form bends, and the first section has a feeding end. A first slot is formed between the first ground radiator, the first section, the second section, and a part of the third section. A width and length of the first slot are associated with a center frequency and impedance matching of a high frequency band.

Abstract: Cavity resonators are promising resources for quantum technology, while native nonlinear interactions for cavities are typically too weak to provide the level of quan-turn control required to deliver complex targeted operations. Here we investigate a scheme to engineer a target Hamiltonian for photonic cavities using ancilla qubits. By off-resonantly driving dispersively coupled ancilla qubits, we develop an optimized approach to engineering an arbitrary photon-number dependent (PND) Hamiltonian for the cavities while minimizing the operation errors. The engineered Hamiltonian admits various applications including canceling unwanted cavity self-Kerr interac-tions, creating higher-order nonlinearities for quantum simulations, and designing quantum gates resilient to noise. Our scheme can be implemented with coupled microwave cavities and transmon qubits in superconducting circuit systems.

Abstract: An antenna module disposed on a substrate having a first and a second surface opposite to each other includes a microstrip line, a first radiator, a ground radiator and a ground plane. The microstrip line, the first radiator and the ground radiator are disposed on the first surface. The microstrip line includes a first and a second end opposite to each other. The first end includes a first feeding end. The first radiator is connected to the second end of the microstrip line. The ground radiator surrounds the microstrip line and the first radiator and has a first opening and two opposite grounding ends. The first end of the microstrip line is located in the first opening. A gap is formed between each grounding end and the first feeding end. The ground plane is disposed on the second surface. The ground radiator is connected to the ground plane.

Abstract: An electronic package module and the method for fabrication of the same are provided. The method for fabricating the electronic package module includes providing a circuit substrate. An interposer frame and a first electronic component are disposed on the circuit substrate, and a shielding material with an opening overlapping the electronic component is disposed on the interposer frame. Subsequently, with the shielding material being as a mask, the molding material is filled into through the opening, thereby forming the molding layer encapsulating the electronic component. After forming the molding layer, the shielding material is removed, so that an interface of the interposer frame is exposed. Therefore, the solder ball can be disposed on the interface of the interposer frame without further machining of the molding layer.

Abstract: An antenna module includes a transceiver chip, a transmitting array antenna, a receiving array antenna, two bandpass filters, and two capacitors. The transmitting array antenna and the receiving array antenna are symmetrically disposed at the two opposite sides of the transceiver chip. One of the bandpass filters is disposed between the transceiver chip and the transmitting array antenna and connected to the transceiver chip and the transmitting array antenna. The other bandpass filter is disposed between the transceiver chip and the receiving array antenna and connected to the transceiver chip and the receiving array antenna. One of the capacitors is disposed between the transmitting array antenna and the corresponding bandpass filter and connected to the transmitting array antenna and the corresponding bandpass filter. The other capacitor is disposed between the receiving array antenna and the corresponding bandpass filter and connected to the receiving array antenna and the corresponding bandpass filter.

Abstract: An interest token processing system integrated with blockchain and method thereof are disclosed. In the interest token processing system, a smart contract is deployed in blockchain environment, and interest tokens of a product or a service and a recycling condition of the interest tokens are generated for a specified target; when the product or the service is obtained through the interest tokens, the smart contract is executed to realize a part of the interest tokens based on the recycling condition and receive another part of the interest tokens for further distribution; during an operation of further distribution, the received interest tokens are distributed based on a ratio of a held amount of the interest tokens to a circulation amount of the interest tokens. Therefore, the technical effect of enabling the tokens to have usability and interest right can be achieved.

Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.

Abstract: An antenna module includes a first metal plate and a frame body. The frame body surrounds the first metal plate. The frame body includes a first antenna radiator, a second antenna radiator, a third antenna radiator, a first breakpoint and a second breakpoint. The first antenna radiator includes a first feeding end and excites a first frequency band. The second antenna radiator includes a second feeding end and excites a second frequency band. The third antenna radiator includes a third feeding end and excites a third frequency band. The first breakpoint is located between the first antenna radiator and the second antenna radiator. The second breakpoint is located between the second antenna radiator and the third antenna radiator. An electronic device including the above-mentioned antenna module is also provided.

Abstract: Provided is a method of manufacturing a memory device and a patterning method. The patterning method includes following steps. A control structure including stop layers and oxide layers stacked alternately, a hard mask layer, and a mask pattern are sequentially formed on a target layer. A photoresist layer is formed in the mask pattern on the hard mask layer. A portion of the hard mask layer and a portion of the control structure are removed to form first openings by using the photoresist layer and the mask pattern as a mask. The photoresist layer and the hard mask layer are removed to form a second opening having a bottom surface higher than that of the first openings. At least one etching process is performed so that the first and second openings extend into and divide the control structure and the target layer into stack structures.

Abstract: Disclosed is a tungsten-doped lithium manganese iron phosphate-based particulate for a cathode of a lithium-ion battery. The particulates include a composition represented by a formula of LixMn0.998-y-zFeyMzW0.002PaO4a±p/C, wherein x, y, z, a, p, and M are as defined herein. Also disclosed is a powdery material including the particulates, and a method for preparing the powdery material.

Abstract: System, methods, and other embodiments described herein relate to training a scene simulator for rendering 2D scenes using data from real and simulated agents. In one embodiment, a method includes acquiring trajectories and three-dimensional (3D) views for multiple agents from observations of real vehicles. The method also includes generating a 3D scene having the multiple agents using the 3D views and information from simulated agents. The method also includes training a scene simulator to render scene projections using the 3D scene. The method also includes outputting a 2D scene having simulated observations for a driving scene using the scene simulator.

Abstract: A testkey structure includes a substrate, a control gate, a metal gate, a dielectric structure, a source line, and a drain line. The control gate is disposed over the substrate and includes a first region and a second region. The second region is adjacent to the first region. The first region has a first conductivity type, and the second region has a second conductivity type. The second conductivity type is different from the first conductivity type. The metal gate is disposed over the control gate. The dielectric structure is embedded in the metal gate and divides the metal gate into a first part and a second part. The dielectric structure is adjacent to the junction between the first region and the second region. The dielectric structure is in contact with the control gate. The source line and the drain line are disposed on opposite sides of the control gate.

Abstract: A method of a circuit signal enhancement of a circuit board comprises the following steps: forming a first substrate body with a first signal transmission circuit layer and a second substrate body with a second signal transmission circuit layer; forming a first signal enhancement circuit layer and a second signal enhancement circuit layer on the first substrate body and the second substrate body; forming a third substrate body with a third signal transmission circuit layer and a fourth substrate body with a fourth signal transmission circuit layer on the carrier; separating the third substrate body and the fourth substrate body from the carrier; combining the first signal transmission circuit layer and the third signal transmission circuit layer through the first signal enhancement circuit layer; and combining the second signal transmission circuit layer and the fourth signal transmission circuit layer through the second signal enhancement circuit layer.

Abstract: A micro light emitting diode structure including an epitaxial structure, a first insulating layer and a second insulating layer is provided. The epitaxial structure includes a first type semiconductor layer, a light emitting layer and a second type semiconductor layer. The first type semiconductor layer, the light emitting layer and a first portion of the second type semiconductor layer form a mesa. A second portion of the second type semiconductor layer is recessed relative the mesa to form a mesa surface. The first insulating layer covers from a top surface of the mesa to the mesa surface along a first side surface of the mesa, and exposes the second side surface. The second insulating layer directly covers a second side surface of the second portion, wherein a thickness ratio of the first insulating layer to the second insulating layer is between 10 and 50.

Abstract: An electronic device includes a metal back cover, a metal frame, and two radiators. The metal frame disposed at a side of the metal back cover includes two disconnecting parts, a second slot, and two connecting parts. A first slot is formed between each of the disconnecting parts and the metal back cover. The second slot is formed between the two disconnecting parts. The two connecting parts are connected to a side away from the second slot of the two disconnecting parts respectively and are connected to the metal back cover. Each of the radiators connects the metal back cover to the corresponding disconnecting part over the first slot. The two radiators are disposed symmetrically based on the second slot. Each radiator is coupled with the corresponding disconnecting part, the corresponding connecting part, and the metal back cover to resonate a first, a second, and a third frequency band.

Abstract: A memory controller coupled to a memory device for accessing the memory device and includes a Universal Asynchronous Receiver/Transmitter (UART) and a microprocessor. The microprocessor is coupled to the UART and configured to control access operations of the memory device. The microprocessor is configured to perform an interrupt service routine in response to an interrupt. When performing the interrupt service routine, the microprocessor is configured to determine whether a predetermined signal has been received by a specific pin and when determining that the predetermined signal has been received by the specific pin, the microprocessor is configured to output a debug message through a transmitting terminal of the UART.

Abstract: A package structure and a manufacturing method for the same are provided. The package structure includes a circuit, a mold sealing layer, a conductive metal board, and a conductive layer. The circuit board includes a substrate and a first electronic element disposed on the substrate. The mold sealing layer is disposed on the substrate and covers the first electronic element. The mold sealing layer has a top surface, a bottom surface corresponding to the top surface, and a side surface connected between the top surface and the bottom surface. The conductive metal board is disposed on the top surface and adjacent to the first electronic element. The conductive layer is disposed on the side surface and electrically connected to the conductive metal board. The conductive metal board and the conductive layer are each an independent component.

Abstract: A modified electrode, manufacturing method thereof and use thereof are provided. The manufacturing method includes steps of: mixing a carbon nanomaterial with 2,2?-azino-bis(3-ethylbenzothiazoline-6-sulfonic acid), followed by drop-casting on a screen-printed carbon electrode, to obtain carbon material modified electrodes; and electrochemically pre-treating the carbon material modified electrodes by cyclic voltammetry technique, constant potential technique, or constant current technique to obtain a modified electrode. 3-Ethyl-6-sulfonate benzothiazolinone imine and 3-ethyl-6-sulfonate benzothiazolone compound are formed on a surface of the modified electrode, and the modified electrode is used for protein analysis, protein immobilization and related biosensor, electrochemical catalysis or biofuel cells.

Abstract: An asset right management system based on blockchain and a method thereof are disclosed. In the system, an asset smart contract of the asset is pre-deployed on a blockchain network, and an asset smart contract is executed to generate a fungible ownership token representing the ownership of the asset, and generate a non-fungible use-right token representing the right to use the asset, based on the ownership token; when the asset smart contract receives proceeds which is obtained through a transaction of the use-right token, the asset smart contract calculates and transfers an profit-sharing amount of each owner, so as to achieve the technical effect of improving convenience in rights management and income of the asset.