Patents by Inventor Hsuan Wang

Hsuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11469504
    Abstract: An electronic device and an antenna structure thereof are provided. The antenna structure includes a first radiating member, a feeding member disposed on the first radiating member, a second radiating member, and a grounding member. A first predetermined gap is between the feeding member and the first radiating member. The feeding member, the first predetermined gap, and the first radiating member resonate to generate a low frequency band and a high frequency band. The second radiating member including a main body and a grounding part is disposed on the first radiating member. A second predetermined gap is between the main body and the first radiating member. The grounding part, the main body, and the second predetermined gap resonate to increase a bandwidth of the low frequency band. The grounding member is disposed on the first radiating member and electrically connected to the grounding part.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: October 11, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Shih-Keng Huang, Tse-Hsuan Wang, Yi-Ru Yang, Hau-Yuen Tan
  • Publication number: 20220320126
    Abstract: Provided is a memory device including a substrate, a plurality of first stack structures, and a plurality of second stack structures. The substrate includes an array region and a periphery region. The first stack structures are disposed on the substrate in the array region. Each first stack structure sequentially includes: a first tunneling dielectric layer, a first floating gate, a first inter-gate dielectric layer, a first control gate, a first metal layer, a first cap layer, and the first stop layer. The second stack structures are disposed on the substrate in the periphery region. Each second stack structure sequentially includes: a second tunneling dielectric layer, a second floating gate, a second inter-gate dielectric layer, a second control gate, a second metal layer, a second cap layer, and the second stop layer. The first stack structures have a pattern density greater than a pattern density of the second stack structures.
    Type: Application
    Filed: August 26, 2021
    Publication date: October 6, 2022
    Applicant: Winbond Electronics Corp.
    Inventor: Chung-Hsuan Wang
  • Publication number: 20220293526
    Abstract: A routing structure between dies is provided, including a trace layer, disposed on a substrate, wherein a plurality of routing paths is embedded in the trace layer. In addition, a first die and a second die are disposed on the trace layer and connected by the routing paths. A spacing gap between the first die and the second die is along a first direction and interfacing edges of the first die and the second die are extending along a second direction perpendicular to the first direction. Each of the routing paths includes a first straight portion in parallel to connect to the interfacing edges. The first straight portion has a slant angle with respect to the first direction other than 0° and 90°.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 15, 2022
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chieh Liao, Hao-Yu Tung, Yu-Cheng Sun, Ming-Hsuan Wang, Igor Elkanovich
  • Publication number: 20220280723
    Abstract: A power pack assembly for a medicament delivery device is presented having a housing extending along a longitudinal axis and having a proximal and a distal end, a container carrier unit arranged longitudinally and bi-directionally movable in relation to the housing, a plunger pusher releasably connected to the container carrier unit, and an actuator unit connected to the plunger pusher, wherein the actuator unit is configured to drive the plunger pusher in a sequence in which the plunger pusher and the container unit are moved together distally relative to the housing until a virtual distal stop is met. Proximal movement of the plunger pusher causes the container carrier unit to interact with a proximal stop element of the housing whereby the plunger pusher is released from the container carrier unit and the plunger pusher continues to move proximally a further distance.
    Type: Application
    Filed: September 7, 2020
    Publication date: September 8, 2022
    Inventors: Hsuan Wang, Jared Schwartzentruber
  • Patent number: 11430768
    Abstract: A chip package structure includes a wiring board, a first chip, a second chip, a thermally conductive material, a molding compound and a heat dissipation part. The wiring board includes a plurality of circuit pads. The first chip is mounted on the wiring board and is electrically connected to at least one of the circuit pads. The first chip is located between the second chip and the wiring board. The thermally conductive material is located on the wiring board and penetrates the second chip and the first chip to extend to the wiring board. The molding compound is disposed on the wiring board, and the heat dissipation part is disposed on the molding material and thermally coupled to the thermally conductive material.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: August 30, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Tzu-Hsuan Wang, Chen-Hsien Liu
  • Patent number: 11418221
    Abstract: The disclosure provides a method and a polar code decoder for determining a to-be-flipped bit position when performing a successive cancellation list flip operation. The method includes: obtaining a polar code decoding tree generated by performing a successive cancellation list (SCL) operation on a polar code segment, and the polar code segment includes multiple bit positions, and each bit position in the polar code decoding tree includes multiple surviving paths and multiple pruned paths; in a post-processing stage for the SCL operation, estimating a correct path probability of each of the surviving paths and the pruned paths of the i-th bit position and accordingly estimating a reliability for the i-th bit position; selecting a specific bit position among the bit positions based on the reliability of each bit position; and performing an SCL flip operation on the polar code decoding tree based on the specific bit position.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: August 16, 2022
    Assignee: National Tsing Hua University
    Inventors: Chung-Hsuan Wang, Yi-Han Pan, Yu-Heng Lin, Yeong-Luh Ueng, Chin-Liang Wang
  • Patent number: 11410901
    Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a circuit board, a barrier structure and a molding layer. The circuit board includes a substrate and a component disposed on the substrate. The substrate includes a molding area and a non-molding area, and the component is disposed on the molding area. The barrier structure is disposed on the substrate and located between the molding area and the non-molding area. The barrier structure has a first predetermined height. The molding layer is disposed on the molding area and covers the component. The molding layer has a second predetermined height. The first predetermined height of the barrier structure is less than or equal to the second predetermined height of the molding layer.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: August 9, 2022
    Assignee: WISTRON NEWEB CORPORATION
    Inventors: Lee-Cheng Shen, Ying-Po Hung, Chao-Chieh Chan, Chao-Hsuan Wang
  • Publication number: 20220208641
    Abstract: A power module package structure includes, from top to bottom, a layer of power chips, an upper bonding layer, a thermally-conductive and electrically-insulating composite layer, and a heat dissipation layer. The thermally-conductive and electrically-insulating composite layer contains an insulating layer and an upper copper layer that is formed on the insulating layer. One or more layers of upper packaging materials are covered over the layer of power chips and the upper bonding layer and are in contact with an upper surface of the upper copper layer. One or more layers of lower packaging materials are in contact with the insulating layer and are in contact with sidewalls of the upper copper layer. The lower packaging material has a higher rigidity than the upper packaging material.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Inventors: TZE-YANG YEH, TZU-HSUAN WANG, CHING-MING YANG
  • Publication number: 20220200786
    Abstract: An anonymous disclose and many-to-many recognition system based on blockchain and identity confirmation allowance and a method thereof are disclosed. In the system, an exposing host generates a one-time address and encrypt the disclosure data into the encrypted data, write the encrypted data into the blockchain; an identity confirmation host generates a valid flag, and an announcement host decrypts the encrypted data to generate a corresponding receipt flag, and garbles a correspondence between the decrypted disclosure data and the corresponding one-time address, to generate and write a shuffled recognition announcement to a blockchain, so that when the exposing host detects the presence of the self-owned disclosure data and one-time address in the shuffled recognition announcement, the exposing host writes a recognition flag into the blockchain. Therefore, the technical effect of improving anonymity and allowing identity confirmation can be achieved.
    Type: Application
    Filed: June 15, 2021
    Publication date: June 23, 2022
    Inventors: Chen-Hsuan WANG, Jiann-Min YANG, Scott MIAU
  • Publication number: 20220189923
    Abstract: A chip package structure includes a wiring board, a first chip, a second chip, a thermally conductive material, a molding compound and a heat dissipation part. The wiring board includes a plurality of circuit pads. The first chip is mounted on the wiring board and is electrically connected to at least one of the circuit pads. The first chip is located between the second chip and the wiring board. The thermally conductive material is located on the wiring board and penetrates the second chip and the first chip to extend to the wiring board. The molding compound is disposed on the wiring board, and the heat dissipation part is disposed on the molding material and thermally coupled to the thermally conductive material.
    Type: Application
    Filed: February 23, 2021
    Publication date: June 16, 2022
    Inventors: Tzu-Hsuan WANG, Chen-Hsien LIU
  • Patent number: 11349213
    Abstract: An antenna structure includes a ground, a first patch, a second patch, a first conductive post, and a second conductive post. The first patch is spaced apart from the ground. The first patch includes a circular slit, a main patch portion and a circular portion. The circular portion and the circular slit surround the main patch portion, and the circular slit is located between the main patch portion and the circular portion. The second patch is disposed between and spaced apart from the ground and the main patch portion. A dimension of the second patch is less than a dimension of the main patch portion. One end of the first conductive post is connected to the second patch. Another end of the first conductive post passes through the ground and is coupled to a signal feeding end. The circular portion is connected to the ground through the second conductive post.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: May 31, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Yi-Ru Yang, Shih-Keng Huang, Chao-Hsu Wu, Tse-Hsuan Wang, Hau Yuen Tan
  • Publication number: 20220166855
    Abstract: The invention relates to a system for development interface and a data transmission method for development interface. The system includes a development board and a host computer. The development board is electrically connected to the host computer by a debug interface. The data format transmitted by host computer includes a header field, an address field and a data field. When performing mass data transfer, a specific command is set in the header field to lift the restriction for the length of the data field. When the development board receives the specific command, a serial data transmission mode is switched to receive all data of the data field.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 26, 2022
    Inventors: CHENG HSUAN WANG, CHUNG HSIN CHEN
  • Publication number: 20220162744
    Abstract: A sputtering target structure includes a body having a first side and an opposing second side. A first sputtering target is coupled to the first side of the body. The first sputtering target includes a first material. A second sputtering target is coupled to the second side of the body. The second sputtering target includes a second material. A rotation mechanism is coupled to the body and is configured to allow rotation of the body from a first orientation to a second orientation.
    Type: Application
    Filed: February 8, 2022
    Publication date: May 26, 2022
    Applicant: Taiwa Semiconductor Manufacturing Co, Ltd.
    Inventors: Ping-Yuan CHEN, Hung-Cheng CHEN, Chih-Hsuan HSIEH, Yu-Hsuan WANG
  • Patent number: 11337614
    Abstract: A multi-target vital sign detection system includes a transmitter, a receiver and a processor. The transmitter is configured to transmit a millimeter wave signal to a detection area, and the receiver is configured to receive a reflecting millimeter wave signal reflected by a plurality of targets in the detection area. The processor is configured to: generate signal strength versus distance data by analyzing the received reflecting millimeter wave signal; perform an extreme value reserving process to generate signal extreme value versus distance data; perform a peak search algorithm to obtain a peak list including a plurality of peak values and a plurality of corresponding peak distances; generate a distance array including a plurality of distance variables; and perform a vital sign detection algorithm to generate multiple sets of vital sign data.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 24, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Tse-Hsuan Wang, Po-Yuan Chen, Chao-Hsu Wu
  • Publication number: 20220149868
    Abstract: The disclosure provides a method and a polar code decoder for determining a to-be-flipped bit position when performing a successive cancellation list flip operation. The method includes: obtaining a polar code decoding tree generated by performing a successive cancellation list (SCL) operation on a polar code segment, and the polar code segment includes multiple bit positions, and each bit position in the polar code decoding tree includes multiple surviving paths and multiple pruned paths; in a post-processing stage for the SCL operation, estimating a correct path probability of each of the surviving paths and the pruned paths of the i-th bit position and accordingly estimating a reliability for the i-th bit position; selecting a specific bit position among the bit positions based on the reliability of each bit position; and performing an SCL flip operation on the polar code decoding tree based on the specific bit position.
    Type: Application
    Filed: January 25, 2021
    Publication date: May 12, 2022
    Applicant: National Tsing Hua University
    Inventors: Chung-Hsuan Wang, Yi-Han Pan, Yu-Heng Lin, Yeong-Luh Ueng, Chin-Liang Wang
  • Patent number: 11316106
    Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact. The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: April 26, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Chung-Hsuan Wang, Yu-Ting Chen, Tz-Hau Guo, Chang-Hsuan Wu, Chiung-Lin Hsu
  • Publication number: 20220121745
    Abstract: A method for labeling object of operating system is adapted to a target object of a target operating system, wherein the target object has a target attribute. The method comprises: generating a default label by a labeling tool according to the target attribute; obtaining a reference object of a reference operating system, wherein the reference object has a reference attribute and a reference label; comparing whether the target attribute and the reference attribute are identical and generating a comparison result; and labeling the target object with the default label, the reference label, or one of a plurality of candidate labels according to the comparison result and a type of the target object.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 21, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tzi-Cker CHIUEH, Yu-Hsuan WANG, Po-Chun CHANG, Yi-Ting CHAO
  • Patent number: 11302601
    Abstract: An IGBT module with a heat dissipation structure and a method for manufacturing the same are provided. The IGBT module with a heat dissipation structure includes a layer of IGBT chips, a bonding layer, a thick copper layer, a thermally-conductive and electrically-insulating layer, and a heat dissipation layer. A portion of the thermally-conductive and electrically-insulating layer is made of a polymer composite material, and a remaining portion of the thermally-conductive and electrically-insulating layer is made of a ceramic material. The thick copper layer is bonded onto the thermally-conductive and electrically-insulating layer by hot pressing. A fillet is formed at a bottom edge of the thick copper layer, and the bottom edge of the thick copper layer is embedded into the thermally-conductive and electrically-insulating layer.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: April 12, 2022
    Assignee: AMULAIRE THERMAL TECHNOLOGY, INC.
    Inventors: Tzu-Hsuan Wang, Tze-Yang Yeh, Chih-Hung Shih
  • Patent number: 11291137
    Abstract: A cooling device includes a cabinet, a coolant circulation mechanism, and a heat exchange mechanism. The coolant circulation mechanism includes a first conduit, a second conduit, a control conduit, and a circulation conduit. The circulation conduit is connected to the cabinet and the heat exchange mechanism. The first conduit and the second conduit are connected to the heat exchange mechanism. The control conduit is connected to the cabinet and selectively connects to the first conduit or the second conduit. When the control conduit connects to the second conduit, coolant from the cabinet flows to the heat exchange mechanism through the second conduit. When the control conduit connects to the first conduit, coolant from the heat exchange mechanism flows to the cabinet through the first conduit. Coolant in the cabinet flows through the circulation conduit to the heat exchange mechanism when a level of the coolant reaches the circulation conduit.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 29, 2022
    Assignee: HONGFUJIN PRECISION ELECTRONICS(TIANJIN)CO., LTD.
    Inventors: Chao-Ke Wei, Hui-Hsuan Wang, Ching-Tang Liu
  • Patent number: 11268186
    Abstract: A sputtering target structure includes a body having a first side and an opposing second side. A first sputtering target is coupled to the first side of the body. The first sputtering target includes a first material. A second sputtering target is coupled to the second side of the body. The second sputtering target includes a second material. A rotation mechanism is coupled to the body and is configured to allow rotation of the body from a first orientation to a second orientation.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Yuan Chen, Hung-Cheng Chen, Chih-Hsuan Hsieh, Yu-Hsuan Wang