Patents by Inventor Hsuan Yang

Hsuan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240097026
    Abstract: A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Inventors: HIDEKI TAKEUCHI, RICHARD BURTON, YUNG-HSUAN YANG
  • Publication number: 20240097567
    Abstract: A conversion control circuit is configured to generate a PWM (pulse width modulation) signal to control a power switch for switching an inductor to convert an input voltage to an output voltage. The steps of generating the PWM signal includes: enabling the PWM signal at a rising edge of a clock signal to turn on the power switch; disabling the PWM signal to turn off the power switch when an on-time exceeds a predetermined minimum on-time and the output voltage has reached an output level; triggering a next rising edge of the clock signal when the off-time exceeds a predetermined minimum off-time, the output voltage has not reached the output level, and a present cycle period of the clock signal has reached a predetermined cycle period.
    Type: Application
    Filed: August 22, 2023
    Publication date: March 21, 2024
    Inventors: Hung-Yu Cheng, Wan-Hsuan Yang, Chi-Hsun Wu
  • Patent number: 11922939
    Abstract: A system and method are disclosed for ignoring a wakeword received at a speech-enabled listening device when it is determined the wakeword is reproduced audio from an audio-playing device. Determination can be by detecting audio distortions, by an ignore flag sent locally between an audio-playing device and speech-enabled device, by and ignore flag sent from a server, by comparison of received audio played audio to a wakeword within an audio-playing device or a speech-enabled device, and other means.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: March 5, 2024
    Assignee: SoundHound AI IP, LLC
    Inventors: Hsuan Yang, Qindí Zhãng, Warren S. Heit
  • Publication number: 20240069594
    Abstract: A portable electronic device including a first body, a second body, a stand, and a hinge structure is provided. The stand has a first pivot part and a second pivot part opposite to the first pivot part, wherein the first pivot part is pivotally connected to the first body, and the second body is pivotally connected to the second pivot part. The hinge structure includes a first bracket secured to the second body, a second bracket secured to the second pivot part of the stand, a first movable base, a first shaft secured to the first bracket and pivoted to the first movable base, a second movable base, a second shaft secured to the first movable base and pivoted to the second movable base, and a sliding shaft fixed to the second movable base and slidably connected to the second bracket.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 29, 2024
    Applicant: Acer Incorporated
    Inventors: Chia-Bo Chen, Yi-Hsuan Yang, Hung-Chi Chen, Wu-Chen Lee
  • Publication number: 20240069069
    Abstract: A probe pin cleaning pad including a foam layer, a cleaning layer, and a polishing layer is provided. The cleaning layer is disposed between the foam layer and the polishing layer. A cleaning method for a probe pin is also provided.
    Type: Application
    Filed: November 10, 2023
    Publication date: February 29, 2024
    Applicant: Alliance Material Co., Ltd.
    Inventors: Chun-Fa Chen, Yu-Hsuen Lee, Ching-Wen Hsu, Chao-Hsuan Yang, Ting-Wei Lin
  • Patent number: 11911911
    Abstract: The present invention relates to a near-site robotic construction system. The system includes a work station situated on a near-site position in a close proximity to a building foundation on which a building is under construction and providing shelter and workspace for at least one robot to work; and a computer-assisted cloud based near-site robotic construction platform installed on a cloud server system and configured to provide for a user to operate through a web browser, import and extract a building information modelling data, and plan a predetermined motion command set partly based on the extracted building information modelling data, wherein the at least one robot is configured to work in accordance with the predetermined motion command set to prefabricate a plurality of components for the building in the work station on the near-site position.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: February 27, 2024
    Assignee: SMART BUILDING TECH CO., LTD.
    Inventors: Shih-Chung Kang, Liang-Ting Tsai, Cheng-Hsuan Yang
  • Patent number: 11911909
    Abstract: The present invention relates to a collision-free path generating method for a robot and an end effector quipped thereon to move. The method includes steps of configuring a virtual working environment, containing a plurality of virtual objects at least including the robot, the end effector and a target object consisting of a plurality of basic members and mapped from a working environment in a reality, in a robot simulator; selecting a level of detail and a pre-determined shape for a collider covering the plurality of virtual objects to determine boundaries for the plurality of objects; randomly sampling a combination of robot configurations; and based on the determine boundaries and the randomly sampled combination of robot configurations, performing a heuristic based pathfinding algorithm to compute a collision-free path for the robot and the end effector quipped thereon to move to the target object accordingly.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: February 27, 2024
    Assignee: SMART BUILDING TECH CO., LTD.
    Inventors: Shih-Chung Kang, Liang-Ting Tsai, Cheng-Hsuan Yang
  • Patent number: 11878009
    Abstract: The present invention relates to a combination of a histone deacetylase (HDAC) inhibitor, chidamide in an acidic salt form, and a nonsteroidal anti-inflammatory drugs (NSAIDs), celecoxib in a basic salt form. The present invention also relates to methods which significantly regulate tumor microenvironment and therefore dramatically improve anti-cancer activity.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: January 23, 2024
    Assignee: GREAT NOVEL THERAPEUTICS BIOTECH & MEDICALS CORPORATION
    Inventors: Jia-Shiong Chen, Mu-Hsuan Yang, Cheng-Han Chou, Yi-Hong Wu, Sz-Hao Chu, Ye-Su Chao, Chia-Nan Chen
  • Publication number: 20240022760
    Abstract: Example aspects of the present disclosure are directed to systems and methods which feature a machine-learned video super-resolution (VSR) model which has been trained using a bi-directional training approach. In particular, the present disclosure provides a compression-informed (e.g., compression-aware) super-resolution model that can perform well on real-world videos with different levels of compression. Specifically, example models described herein can include three modules to robustly restore the missing information caused by video compression. First, a bi-directional recurrent module can be used to reduce the accumulated warping error from the random locations of the intra-frame from compressed video frames. Second, a detail-aware flow estimation module can be added to enable recovery of high resolution (HR) flow from compressed low resolution (LR) frames. Finally, a Laplacian enhancement module can add high-frequency information to the warped HR frames washed out by video encoding.
    Type: Application
    Filed: August 5, 2021
    Publication date: January 18, 2024
    Inventors: Yinxiao Li, Peyman Milanfar, Feng Yang, Ce Liu, Ming-Hsuan Yang, Pengchong Jin
  • Patent number: 11865588
    Abstract: A probe pin cleaning pad including a release layer or composite plate, an adhesive layer, a substrate layer, a cleaning layer, and a polishing layer is provided. The adhesive layer is disposed on the release layer or composite plate. The substrate layer is disposed on the adhesive layer. The cleaning layer is disposed on the substrate layer. The polishing layer is disposed on the cleaning layer. A cleaning method for a probe pin is also provided.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: January 9, 2024
    Assignee: Alliance Material Co., Ltd.
    Inventors: Chun-Fa Chen, Chi-Hua Huang, Yu-Hsuen Lee, Ching-Wen Hsu, Chao-Hsuan Yang, Ting-Wei Lin, Chin-Kai Lin, Chen-Ju Lee
  • Patent number: 11868177
    Abstract: An electronic device includes a host, a main display, an auxiliary display, and a hinge mechanism. The auxiliary display is located between the host and the main display and includes a sliding part and a lifting part. The sliding part is slidably connected to the host. The hinge mechanism includes a first bracket, a second bracket pivotally connected to the first bracket, and a third bracket pivotally connected to the second bracket. The first bracket is secured to the host, and the second bracket is secured to the main display. The third bracket is secured to the lifting part of the auxiliary display.
    Type: Grant
    Filed: December 26, 2022
    Date of Patent: January 9, 2024
    Assignee: Acer Incorporated
    Inventors: Chia-Bo Chen, Cheng-Nan Ling, Wu-Chen Lee, Yi-Hsuan Yang
  • Patent number: 11869968
    Abstract: A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: January 9, 2024
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Richard Burton, Yung-Hsuan Yang
  • Patent number: 11846987
    Abstract: A portable electronic device including a first body, a second body, a stand, and a hinge structure is provided. The stand has a first pivot part and a second pivot part opposite to the first pivot part, wherein the first pivot part is pivotally connected to the first body, and the second body is pivotally connected to the second pivot part. The hinge structure includes a first bracket secured to the second body, a second bracket secured to the second pivot part of the stand, a first movable base, a first shaft secured to the first bracket and pivoted to the first movable base, a second movable base, a second shaft secured to the first movable base and pivoted to the second movable base, and a sliding shaft fixed to the second movable base and slidably connected to the second bracket.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: December 19, 2023
    Assignee: Acer Incorporated
    Inventors: Chia-Bo Chen, Yi-Hsuan Yang, Hung-Chi Chen, Wu-Chen Lee
  • Patent number: 11841743
    Abstract: An electronic device, including a host, a main display, an auxiliary display, and a lifting mechanism, is provided. The main display is pivoted to the host. The auxiliary display is disposed on the host. The lifting mechanism is disposed between the auxiliary display and the host. The lifting mechanism is configured to lift the auxiliary display and maintain a lifting height of the auxiliary display.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: December 12, 2023
    Assignee: Acer Incorporated
    Inventors: Chia-Bo Chen, Yi-Hsuan Yang, Chuan-Hua Wang, Chih-Chun Liu, Wu-Chen Lee
  • Publication number: 20230363717
    Abstract: A method for sampling a signal can accurately cancel a noise signal. The method is performed by a capacitive transimpedance amplifying device that can be applied to a photoplethysmography front-end receiver. The method includes sampling a detection signal and its inversion several times in specific order in a sampling period to obtain a target signal without a noise signal. Specifically, the method includes: sampling the detection signal during a first time slot and a fourth time slot; and sampling the inversion of the detection signal during a second time slot and a third time slot, wherein the first, second, third, and fourth time slots are in sequence and included in the sampling period, the detection signal includes the target signal and the noise signal during the first and fourth time slots, and the detection signal only includes the noise signal during the second and third time slots.
    Type: Application
    Filed: May 12, 2023
    Publication date: November 16, 2023
    Inventors: MING-CHIH KUAN, TZU-HSUAN YANG, LIANG-HUI LI
  • Publication number: 20230363716
    Abstract: An ambient light cancellation circuit functions as a Kth-order filter to filter out an ambient light signal of the detection signal, wherein the K is not fewer than two. The circuit includes a capacitive transimpedance amplifying circuit including an amplifier, a capacitor circuit, and a switch circuit. The capacitor circuit includes one or more capacitive paths coupled in parallel. The switch circuit couples the amplifier with the capacitor circuit in a non-cross manner or a cross manner. The non-cross manner is applied N times to let the capacitor circuit sample the detection signal N times while the detection signal includes a controllable-light signal and the ambient light signal; and the cross manner is applied M times to let the capacitor circuit sample the inversion of the detection signal M times while the detection signal includes the ambient light signal without the controllable-light signal, wherein (N+M) equals (K+1).
    Type: Application
    Filed: May 12, 2023
    Publication date: November 16, 2023
    Inventors: TZU-HSUAN YANG, MING-CHIH KUAN
  • Patent number: 11790550
    Abstract: A method includes obtaining a first plurality of feature vectors associated with a first image and a second plurality of feature vectors associated with a second image. The method also includes generating a plurality of transformed feature vectors by transforming each respective feature vector of the first plurality of feature vectors by a kernel matrix trained to define an elliptical inner product space. The method additionally includes generating a cost volume by determining, for each respective transformed feature vector of the plurality of transformed feature vectors, a plurality of inner products, wherein each respective inner product of the plurality of inner products is between the respective transformed feature vector and a corresponding candidate feature vector of a corresponding subset of the second plurality of feature vectors. The method further includes determining, based on the cost volume, a pixel correspondence between the first image and the second image.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: October 17, 2023
    Assignee: Google LLC
    Inventors: Taihong Xiao, Deqing Sun, Ming-Hsuan Yang, Qifei Wang, Jinwei Yuan
  • Patent number: 11792958
    Abstract: The present disclosure provides a connector assembly comprising a cage and a heat sink. The cage has a receiving space and a wall constituting the receiving space, the wall is formed with a window which is communicated with the receiving space and two latching plates which are provided to two sides of the window and extend away from the receiving space, each latching plate is integrally formed with a latching protrusion, the latching protrusion has a guiding portion and a latching portion, a protruding amount of the guiding portion from the latching plate gradually increases as a distance of the guiding portion from the receiving space decreases, the latching portion is positioned to a tip end surface of the guiding portion.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: October 17, 2023
    Assignee: Molex, LLC
    Inventors: Sheng-Ping Yen, Tsai-Hui Chien, Hui-Hsuan Yang, Kuan-Lin Peng, Vinayakumar Kori
  • Patent number: 11789297
    Abstract: An optical phase shifter array includes: 1st˜nth optical-splitting elements, wherein each has an input end, a first output end and a second output end, and the input end of the 1st optical-splitting element receives an input light and outputs an evenly distributed optical signal to the optical-splitting element of the next stage, and n is a positive integer above 1; a plurality of first optical waveguides respectively connected to the input end of the optical-splitting element odd-numbered of the next stage and the first output end of the optical-splitting element of the previous stage; a plurality of second optical waveguides respectively connected to the input end of the optical-splitting-element even-numbered of the previous stage; and phase shifters of the 1st to the kth stage, which makes the optical signal passing through the optical waveguides produce a phase shift by heating or electro-optic effects.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: October 17, 2023
    Assignee: NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: San-Liang Lee, Tsung-Han Lee, Chia-Hsuan Yang
  • Publication number: 20230263790
    Abstract: The present disclosure generally relates to compounds class I HDAC inhibitors, their production and applications. The compounds possess epigenetic immunomodulatory activities in the tumor microenvironment (TME) and thus inhibit growth of tumor cells.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 24, 2023
    Inventors: Jia-Shiong CHEN, Mu-Hsuan YANG, Yi-Hong WU, Sz-Hao CHU, Cheng-Han CHOU, Ye-Su CHAO, Chia-Nan CHEN