Patents by Inventor Hsun Wang

Hsun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230065045
    Abstract: A method and structure for forming a semiconductor device includes etching back a source/drain contact to define a substrate topography including a trench disposed between adjacent hard mask layers. A contact etch stop layer (CESL) is deposited along sidewall and bottom surfaces of the trench, and over the adjacent hard mask layers, to provide the CESL having a snake-like pattern disposed over the substrate topography. A contact via opening is formed in a dielectric layer disposed over the CESL, where the contact via opening exposes a portion of the CESL within the trench. The portion of the CESL exposed by the contact via opening is etched to form an enlarged contact via opening and expose the etched back source/drain contact. A metal layer is deposited within the enlarged contact via opening to provide a contact via in contact with the exposed etched back source/drain contact.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Shih-Che LIN, Chao-Hsun WANG, Chia-Hsien YAO, Fu-Kai YANG, Mei-Yun WANG
  • Publication number: 20230047601
    Abstract: An infrared thermopile sensor includes a silicon cover having an infrared lens, an infrared sensing chip having duo-thermopile sensing elements, and a microcontroller chip calculating a temperature of an object. The components are in a stacked 3D package to decrease the size of the infrared thermopile sensor. The infrared sensing chip and the microcontroller chip have metal layers to shield the thermal radiation. The conversion from wrist temperature to body core temperature uses detected ambient temperature and fixed humidity or imported humidity level to calculate the body core temperature based on experimental data and curve fitting. The skin temperature compensation can be set differently for different sex gender, different standard deviation of wrist temperature and external relative humidity reading.
    Type: Application
    Filed: August 16, 2021
    Publication date: February 16, 2023
    Inventors: Chein-Hsun WANG, Da-Jun LIN, Chun-Chiang CHEN, Chih-Yung TSAI, Yu-Chih LIANG, Ming LE, Chen-Tang HUANG, Tung-Yang LEE, Jenping KU
  • Publication number: 20230049010
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and nanostructures suspended over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure also includes a contact vertically over the source/drain structure and a first conductive structure vertically over the gate structure. The semiconductor structure also includes a second conductive structure in contact with a top surface of the first conductive structure and a top surface of the contact and including an extending portion laterally sandwiched between the first conductive structure and the contact.
    Type: Application
    Filed: November 1, 2022
    Publication date: February 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Heng WANG, Pang-Chi WU, Chao-Hsun WANG, Fu-Kai YANG, Mei-Yun WANG
  • Publication number: 20230033570
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal gate stack over a substrate and an epitaxial structure over the substrate. The semiconductor device structure also includes a conductive contact electrically connected to the epitaxial structure. A topmost surface of the metal gate stack is vertically disposed between a topmost surface of the conductive contact and a bottommost surface of the conductive contact. The semiconductor device structure further includes a first conductive via electrically connected to the metal gate stack. The topmost surface of the conductive contact is vertically disposed between a topmost surface of the first conductive via and a bottommost surface of the first conductive via. In addition, the semiconductor device structure includes a second conductive via electrically connected to the conductive contact.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh WU, Pang-Chi Wu, Wang-Jung Hsueh, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Patent number: 11563104
    Abstract: A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure over the fin. The semiconductor device also includes a source region and a drain region in the fin and at opposite sides of the gate structure. The semiconductor device further includes a gate spacer on a sidewall of the gate structure. The gate spacer includes an air-gap spacer and a sealing spacer above the air-gap spacer, an upper portion of the gate structure is laterally overlapping with the sealing spacer, and the bottom portion of the gate structure is laterally overlapping with the air gap spacer.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsiung Lin, Pei-Hsun Wang, Chih-Chao Chou, Chia-Hao Chang, Chih-Hao Wang
  • Publication number: 20230011493
    Abstract: A package assembly includes an interposer module on a package substrate, a thermal interface material (TIM) film on the interposer module, and a package lid that includes a plate portion on the TIM film and a step region projecting away from the plate portion and located over the TIM film and over an edge region of the interposer module.
    Type: Application
    Filed: March 29, 2022
    Publication date: January 12, 2023
    Inventors: Ping-Yin HSIEH, Yu-Hsun WANG, Li-Hui CHENG, Szu-Wei LU
  • Patent number: 11532561
    Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
  • Patent number: 11532521
    Abstract: A semiconductor structure includes a first fin, which includes a first plurality of suspended nanostructures vertically stacked over one another, each of the first plurality of suspended nanostructure having a center portion that has a first cross section, and a second fin, which includes a second plurality of suspended nanostructures vertically stacked over one another, the first plurality of suspended nanostructures and the second plurality of suspended nanostructures having different material compositions, each of the second plurality of suspended nanostructure having a center portion that has a second cross section, wherein a shape or an area of the first cross section is different from that of the second cross section.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Sheng Yun, Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Chao Chou, Chun-Hsiung Lin, Pei-Hsun Wang
  • Patent number: 11532717
    Abstract: A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
  • Patent number: 11527614
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a gate structure over a substrate and forming a mask layer covering the gate structure. The method also includes forming a source/drain structure adjacent to the gate structure over the substrate and forming a contact over the source/drain structure. The method also includes forming a dielectric layer over the contact and the mask layer and forming a first trench through the dielectric layer and the mask layer over the gate structure. The method also includes forming a first conductive structure in the first trench and removing an upper portion of the first conductive structure. The method also includes forming a second conductive structure through the dielectric layer and covering the contact and the first conductive structure.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Heng Wang, Pang-Chi Wu, Chao-Hsun Wang, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220384244
    Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.
    Type: Application
    Filed: July 29, 2022
    Publication date: December 1, 2022
    Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu
  • Patent number: 11508822
    Abstract: A source/drain is disposed over a substrate. A source/drain contact is disposed over the source/drain. A first via is disposed over the source/drain contact. The first via has a laterally-protruding bottom portion and a top portion that is disposed over the laterally-protruding bottom portion.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang
  • Publication number: 20220367703
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Kuo-Cheng Chiang, Zhi-Chang Lin, Shih-Cheng Chen, Chih-Hao Wang, Pei-Hsun Wang, Lo-Heng Chang, Jung-Hung Chang
  • Publication number: 20220367701
    Abstract: Methods for manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate a substrate and channel layers vertically stacked over the substrate. The semiconductor structure also includes a dielectric fin structure formed adjacent to the channel layers and a gate structure abutting the channel layers and the dielectric fin structure. The semiconductor structure also includes a source/drain structure attached to the channel layers and a contact formed over the source/drain structure. The semiconductor structure also includes a Si layer covering a portion of a top surface of the source/drain structure. In addition, the Si layer is sandwiched between the dielectric fin structure and the contact.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Chen-Han WANG, Pei-Hsun WANG, Chun-Hsiung LIN, Chih-Hao WANG
  • Publication number: 20220367668
    Abstract: A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure formed across the fin. The semiconductor device also includes a gate spacer formed over a sidewall of the gate structure. The gate spacer includes a sidewall spacer and a sealing spacer formed above the sidewall spacer. In addition, an air gap is vertically sandwiched between the sidewall spacer and the sealing spacer. The semiconductor device further includes a hard mask formed over the gate structure and covering a sidewall of the sealing spacer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsiung LIN, Pei-Hsun WANG, Chih-Chao CHOU, Chia-Hao CHANG, Chih-Hao WANG
  • Publication number: 20220359675
    Abstract: A source/drain is disposed over a substrate. A source/drain contact is disposed over the source/drain. A first via is disposed over the source/drain contact. The first via has a laterally-protruding bottom portion and a top portion that is disposed over the laterally-protruding bottom portion.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang
  • Publication number: 20220359345
    Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 10, 2022
    Inventors: Yu-Hsun Wang, Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20220359399
    Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
  • Publication number: 20220352328
    Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.
    Type: Application
    Filed: December 9, 2021
    Publication date: November 3, 2022
    Inventors: Shih-Che Lin, Po-Yu Huang, I-Wen Wu, Chen-Ming Lee, Chia-Hsien Yao, Chao-Hsun Wang, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220341789
    Abstract: An infrared thermopile sensor includes a silicon cover having an infrared lens, an infrared sensing chip having duo-thermopile sensing elements, and a microcontroller chip calculating a temperature of an object. The components are in a stacked 3D package to decrease the size of the infrared thermopile sensor. The infrared sensing chip and the microcontroller chip have metal layers to shield the thermal radiation. To measure object temperature accurately under acute change in environmental temperature, this disclosure uses the duo-thermopile sensing elements, that one is the active unit for measuring the object temperature and another one is the dummy unit for compensating the effect from the package structure.
    Type: Application
    Filed: May 20, 2021
    Publication date: October 27, 2022
    Inventors: Wen-Chie HUANG, Yu-Chih LIANG, Chein-Hsun WANG, Ming LE, Chen-Tang HUANG, Chein-Hsing YU, Tung-Yang LEE, Jenping KU