Patents by Inventor Hsun YANG

Hsun YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978664
    Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu
  • Publication number: 20240131819
    Abstract: A thermally conductive board includes a first metal layer, a second metal layer, and a thermally conductive layer. The material of the first metal layer includes copper, and the first metal layer has a first top surface and a first bottom surface opposite to the first top surface. A first metal coating layer covers the first bottom surface. The material of the second metal layer includes copper, and the second metal layer has a second top surface and a second bottom surface opposite to the second top surface. A second metal coating layer covers the second top surface and faces the first metal coating layer. The thermally conductive layer is an electrically insulator laminated between the first metal coating layer and the second metal coating layer.
    Type: Application
    Filed: May 3, 2023
    Publication date: April 25, 2024
    Inventors: KAI-WEI LO, WEN-FENG LEE, HSIANG-YUN YANG, KUO-HSUN CHEN
  • Publication number: 20240136383
    Abstract: A semiconductor device includes a single-layered dielectric layer, a conductive line, a conductive via and a conductive pad. The conductive line and the conductive via are disposed in the single-layered dielectric layer. The conductive pad is extended into the single-layered dielectric layer to electrically connected to the conductive line.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
  • Patent number: 11967611
    Abstract: A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of AxB1-xO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hai-Dang Trinh, Yi Yang Wei, Fa-Shen Jiang, Bi-Shen Lee, Hsun-Chung Kuang
  • Patent number: 11961886
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and nanostructures suspended over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure also includes a contact vertically over the source/drain structure and a first conductive structure vertically over the gate structure. The semiconductor structure also includes a second conductive structure in contact with a top surface of the first conductive structure and a top surface of the contact and including an extending portion laterally sandwiched between the first conductive structure and the contact.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Heng Wang, Pang-Chi Wu, Chao-Hsun Wang, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240097567
    Abstract: A conversion control circuit is configured to generate a PWM (pulse width modulation) signal to control a power switch for switching an inductor to convert an input voltage to an output voltage. The steps of generating the PWM signal includes: enabling the PWM signal at a rising edge of a clock signal to turn on the power switch; disabling the PWM signal to turn off the power switch when an on-time exceeds a predetermined minimum on-time and the output voltage has reached an output level; triggering a next rising edge of the clock signal when the off-time exceeds a predetermined minimum off-time, the output voltage has not reached the output level, and a present cycle period of the clock signal has reached a predetermined cycle period.
    Type: Application
    Filed: August 22, 2023
    Publication date: March 21, 2024
    Inventors: Hung-Yu Cheng, Wan-Hsuan Yang, Chi-Hsun Wu
  • Patent number: 11922710
    Abstract: A character recognition method includes the following operations: determining that the image of character to be identified corresponds to a matching character of several registered characters according to several vector distances to be identified between a vector of an image of character to be identified and several vectors of several registered character images of several registered characters, and storing a matching vector distance between the vector of the image of character to be identified and a vector of the matching character by a processor; and storing a data of the matching character according to the image of character to be identified when the matching vector distance is less than a vector distance threshold by the processor.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 5, 2024
    Assignee: Realtek Semiconductor Corporation
    Inventors: Chien-Hao Chen, Chao-Hsun Yang, Shih-Tse Chen
  • Publication number: 20240072667
    Abstract: A switching regulator includes a boost power stage circuit and a control circuit. The boost power stage circuit includes: at least one power switch configured to switch a terminal of an inductor according to an operation signal during a normal operation period, such that the terminal of the inductor is switched between an output voltage and ground level; and a power line switch connected in series to the inductor between the input voltage and the output voltage. The power line switch is turned OFF when the output voltage is short to ground level, to prevent a short current from flowing from input voltage to ground level. The control circuit generates the operation signal according to the output voltage and determines whether the power line switch is P-type or N-type MOS device, so as to turn OFF the power line switch when the output voltage is short to ground level.
    Type: Application
    Filed: July 25, 2023
    Publication date: February 29, 2024
    Inventors: Pao-Hsun Yu, Shei-Chie Yang, Yuan-Yen Mai, Cheng-Hung Hsu
  • Patent number: 11916127
    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Yang Wei, Bi-Shen Lee, Hsin-Yu Lai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
  • Patent number: 11734956
    Abstract: The present invention provides a processing circuit applied to a face recognition system, which includes a characteristic value calculation module, a determination circuit and a threshold value calculation module.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: August 22, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chien-Hao Chen, Chao-Hsun Yang, Shih-Tse Chen
  • Publication number: 20230156167
    Abstract: An image recognition system includes a color conversion module and a target recognition module. The color conversion module is configured to convert a gray-level image into a preset color image according to a conversion function. The target recognition module includes a machine learning algorithm, and the machine learning algorithm includes a plurality of functions and a plurality of parameters. The machine learning algorithm receives the preset color image, and outputs a recognition result according to the functions and the parameters, the recognition result including an existent target or a null target.
    Type: Application
    Filed: April 8, 2022
    Publication date: May 18, 2023
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Wei-Hsiang Shen, Kai-Chun Su, Tsung-Hsuan Li, Chao-Hsun Yang, Shih-Tse Chen
  • Publication number: 20230154223
    Abstract: A method of performing person re-identification includes: obtaining a person feature vector according to an extracted image containing a person; obtaining state information of the person according to a state of the person in the extracted image; comparing the person feature vector with a plurality of registered person feature vectors in a database; when the person feature vector successfully matches a first registered person feature vector of the plurality of registered person feature vectors, identifying the person as a first identity corresponding to the first registered person feature vector; and selectively utilizing the person feature vector to update one of the first registered person feature vector and at least one second registered person feature vector that correspond to the first identity according to the state information.
    Type: Application
    Filed: March 3, 2022
    Publication date: May 18, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventors: Chien-Hao Chen, Chao-Hsun Yang, Chih-Wei Wu, Shih-Tse Chen
  • Publication number: 20230154017
    Abstract: A method used for object tracking includes: using a specific object model to generate a first vector of a first ratio object and a second vector of a second ratio object of an image in an object detection bounding box of a specific frame; generating an identity label of an object within the bounding box according to the first vector, the second vector, and M first ratio reference vectors and M second ratio reference vectors stored in an object vector database.
    Type: Application
    Filed: March 3, 2022
    Publication date: May 18, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventors: Chih-Wei Wu, Chien-Hao Chen, Chao-Hsun Yang, Shih-Tse Chen
  • Patent number: 11636823
    Abstract: A method of handling signal transmission applicable to a display system includes a plurality of steps. The steps include transmitting a reset signal embedded in a first data signal to each of at least one source driver via a first data channel, generating a first control signal for setting the at least one source driver, and transmitting the first control signal embedded in a second data signal to each of the at least one source driver via a second data channel when the reset signal is transmitted via the first data channel.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: April 25, 2023
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Shun-Hsun Yang, Tse-Hung Wu
  • Publication number: 20230112822
    Abstract: A character recognition method includes the following operations: determining that the image of character to be identified corresponds to a matching character of several registered characters according to several vector distances to be identified between a vector of an image of character to be identified and several vectors of several registered character images of several registered characters, and storing a matching vector distance between the vector of the image of character to be identified and a vector of the matching character by a processor; and storing a data of the matching character according to the image of character to be identified when the matching vector distance is less than a vector distance threshold by the processor.
    Type: Application
    Filed: April 18, 2022
    Publication date: April 13, 2023
    Inventors: Chien-Hao CHEN, Chao-Hsun YANG, Shih-Tse CHEN
  • Patent number: 11602908
    Abstract: The present disclosure provides a method of mesh generation for an RTM process, including operations of: obtaining a geometry of a target object; generating a solid mesh of the target object according to the geometry; obtaining material characteristics of the target object; assembling a runner mesh with the solid mesh, wherein the runner mesh has grid dimensions different from those of the solid mesh; determining process parameters of the RTM process; and generating a forecasted result of the RTM process according to the solid mesh, the runner mesh, the process parameters, and the material characteristics. Generating the solid mesh includes operations of: dividing the geometry into modules; generating a first and second modular meshes corresponding to a first and second modules, wherein the second modular mesh abuts the first modular mesh, and the second modular mesh has grid dimensions different from those of the first modular mesh.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 14, 2023
    Assignee: CORETECH SYSTEM CO., LTD.
    Inventors: Ching-Kai Chou, Chien-Ting Wu, Hsun Yang, Li-Hsuan Shen, Chih-Chung Hsu, Chia-Hsiang Hsu, Rong-Yeu Chang
  • Publication number: 20230058453
    Abstract: The present disclosure provides a method of mesh generation for an RTM process, including operations of: obtaining a geometry of a target object; generating a solid mesh of the target object according to the geometry; obtaining material characteristics of the target object; assembling a runner mesh with the solid mesh, wherein the runner mesh has grid dimensions different from those of the solid mesh; determining process parameters of the RTM process; and generating a forecasted result of the RTM process according to the solid mesh, the runner mesh, the process parameters, and the material characteristics. Generating the solid mesh includes operations of: dividing the geometry into modules; generating a first and second modular meshes corresponding to a first and second modules, wherein the second modular mesh abuts the first modular mesh, and the second modular mesh has grid dimensions different from those of the first modular mesh.
    Type: Application
    Filed: December 29, 2021
    Publication date: February 23, 2023
    Inventors: Ching-Kai CHOU, Chien-Ting WU, Hsun YANG, Li-Hsuan SHEN, Chih-Chung HSU, Chia-Hsiang HSU, Rong-Yeu CHANG
  • Publication number: 20230041693
    Abstract: A method of data augmentation is provided. The method includes the following operations: selecting an original image from an original dataset including label data configured to indicate a labeled area of the original image; selecting at least part of content, located in the labeled area, of the original image as a first target image; generating a first sample image according to the first target image, in which the first sample image includes the first target image and a first border pattern different from the first target image, and the content, located in the labeled area, of the original image is free from including at least part of the first border pattern; and incorporating the first sample image into a sample dataset, in which the sample dataset is configured to be inputted to a machine learning model.
    Type: Application
    Filed: May 5, 2022
    Publication date: February 9, 2023
    Inventors: Chao-Hsun YANG, Chun-Chang WU, Shih-Tse CHEN
  • Patent number: 11495006
    Abstract: An object detection method and an associated electronic device are provided, wherein the object detection method includes: utilizing an image processing circuit to determine whether motion occurs in an image to generate a determination result; selectively utilizing a specific bounding box to identify a target object to generate an identification result according to the determination result, wherein the specific bounding box represents a location of the target object in a previous image; and selectively updating information of the specific bounding box according to the identification result.
    Type: Grant
    Filed: May 3, 2020
    Date of Patent: November 8, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chao-Hsun Yang, Shang-Lun Chan, Shih-Tse Chen, Chien-Hao Chen
  • Publication number: 20220318543
    Abstract: The present invention provides a processing circuit applied to a face recognition system, which includes a characteristic value calculation module, a determination circuit and a threshold value calculation module.
    Type: Application
    Filed: November 11, 2021
    Publication date: October 6, 2022
    Applicant: Realtek Semiconductor Corp.
    Inventors: Chien-Hao Chen, Chao-Hsun Yang, Shih-Tse Chen