Abstract: A three-dimensional non-volatile memory structure including a substrate, a stacked structure, a charge storage pillar, a channel pillar, and a ferroelectric material pillar is provided. The stacked structure is disposed on the substrate and includes a plurality of conductive layers and a plurality of first dielectric layers, and the conductive layers and the first dielectric layers are alternately stacked. The charge storage pillar is disposed in the stacked structure. The channel pillar is disposed inside the charge storage pillar. The ferroelectric material pillar is disposed inside the channel pillar.

Abstract: The disclosure provides a thermoelectric conversion structure and its use in heat dissipation device. The thermoelectric conversion structure includes a thermoelectric element, a first electrode and an electrically conductive heat-blocking layer. The thermoelectric element includes a first end and a second end opposite to each other. The first electrode is located at the first end of the thermoelectric element. The electrically conductive heat-blocking layer is between the thermoelectric element and the first electrode.

Abstract: A semiconductor device for ultra-high voltage (UHV) operation disclosed in the present invention includes a substrate having a normally-on channel, a negative capacitance material layer, an electrode, a source and a drain. The negative capacitance material layer is disposed over the substrate and capable of adjusting the threshold voltage of the semiconductor device so as to transform the normally-on channel into a normally-off channel and change the transistor characteristics of the semiconductor device from a depletion mode to an enhance mode. In addition, the semiconductor device also includes a gate dielectric layer made of high-k material between the negative capacitance material layer, a gate layer between the gate dielectric layer and the negative capacitance material layer and an ion implantation layer in the substrate under the gate. Furthermore, the aforementioned technical features or structures can be formed in a semiconductor device having a gate-recessed structure.

Abstract: The invention provides a semiconductor device including a substrate, a first dielectric layer, a conductive layer, a ferroelectric material layer, and a charge-trapping layer. The first dielectric layer is disposed on the substrate. The conductive layer is disposed on the first dielectric layer. The ferroelectric material layer and the charge-trapping layer are disposed between the first dielectric layer and the conductive layer by stacking. The semiconductor device of the invention has better memory characteristics and transistor characteristics.

Abstract: A semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an interfacial layer over the semiconductor substrate, the interfacial layer having a capacitive effective thickness of less than 1.37 nanometers (nm). The semiconductor structure further includes a high-k dielectric layer over the interfacial layer.

Abstract: A thin film transistor and a manufacturing method for the same are provided. The thin film transistor comprises a substrate, a double channel semiconductor layer, a semiconductor passivation layer, a gate, a gate dielectric layer, a source and a drain. The double channel semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is made of a metallic oxide semiconductor material and formed above the substrate. The second semiconductor layer is made of the metallic oxide semiconductor material doped by an oxygen gettering metal and formed on the first semiconductor layer. The semiconductor passivation layer is formed on the second semiconductor layer. The gate is formed above the substrate. The gate dielectric layer is formed between the gate and the double channel semiconductor layer.

Abstract: A semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an interfacial layer over the semiconductor substrate, the interfacial layer having a capacitive effective thickness of less than 1.37 nanometers (nm). The semiconductor structure further includes a high-k dielectric layer over the interfacial layer.

Abstract: A method of performing an ultraviolet (UV) curing process on an interfacial layer over a semiconductor substrate, the method includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 700° C. Another method of performing an annealing process on an interfacial layer over a semiconductor substrate, the second method includes supplying a gas flow rate ranging from 10 sccm to 5 slm, wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 600° C.

Abstract: Resistive random access memory (RRAM) using stacked dielectrics and a method for manufacturing the same are disclosed, where a setting power of only 4 ?W, an ultra-low reset power of 2 nW, good switching uniformity and excellent cycling endurance up to 5×109 cycles were achieved simultaneously. Such record high performances were reached in a Ni/GeOx/nano-crystal-TiO2/TaON/TaN RRAM device, where the excellent endurance is 4˜6 orders of magnitude larger than existing Flash memory. The very long endurance and low switching energy RRAM is not only satisfactory for portable SSD in a computer, but may also create new applications such as being used for a Data Center to replace high power consumption hard discs.

Abstract: A method of performing an ultraviolet (UV) curing process on an interfacial layer over a semiconductor substrate, the method includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 700° C. Another method of performing an annealing process on an interfacial layer over a semiconductor substrate, the second method includes supplying a gas flow rate ranging from 10 sccm to 5 slm, wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 600° C.

Abstract: This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.

Abstract: Resistive random access memory (RRAM) using stacked dielectrics and a method for manufacturing the same are disclosed, where a setting power of only 4 ?W, an ultra-low reset power of 2 nW, good switching uniformity and excellent cycling endurance up to 5×109 cycles were achieved simultaneously. Such record high performances were reached in a Ni/GeOx/nano-crystal-TiO2/TaON/TaN RRAM device, where the excellent endurance is 4˜6 orders of magnitude larger than existing Flash memory. The very long endurance and low switching energy RRAM is not only satisfactory for portable SSD in a computer, but may also create new applications such as being used for a Data Center to replace high power consumption hard discs.

Abstract: This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.

Abstract: A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material.

Abstract: A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material.

Abstract: Embodiments of adjusting a line of an image using a determined skew of a sheet are disclosed.

Abstract: The subject invention relates to a method and apparatus for producing stimulated MRI data. In an embodiment, a remote-controlled “smart phantom” can produce simulated data. The simulated data can be acquired from a MRI system. The subject device can generate control signals and send the generated control signals to secondary coils/probes placed in the subject smart phantom. The control signals determine the current flow in the secondary coils/probes, which act as local spin magnetization amplifiers and thus produce regions of variable contrast to noise ratio. The control signals can be generated with various parameters, such as BOLD models, different levels of contrast-to-noise ratio (CNR), signal intensities, and physiological signals. Comparisons can be made with the widely-used simulated data by computers. Validation of the subject smart phantom can be performed with both theoretical analysis and data of human subjects.

Abstract: The subject invention relates to a method and apparatus for producing stimulated MRI data. In an embodiment, a remote-controlled “smart phantom” can produce simulated data. The simulated data can be acquired from a MRI system. The subject device can generate control signals and send the generated control signals to secondary coils/probes placed in the subject smart phantom. The control signals determine the current flow in the secondary coils/probes, which act as local spin magnetization amplifiers and thus produce regions of variable contrast to noise ratio. The control signals can be generated with various parameters, such as BOLD models, different levels of contrast-to-noise ratio (CNR), signal intensities, and physiological signals. Comparisons can be made with the widely-used simulated data by computers. Validation of the subject smart phantom can be performed with both theoretical analysis and data of human subjects.

Abstract: The subject invention pertains to a method of image intensity correction. The subject invention can utilize extrapolation for image intensity correction. The use of extrapolation can reduce the artifacts during intensity correction as compared to traditional methods of intensity correction. The extrapolation can be combined with, for example, homomorphic filtering methods, parametric estimation techniques, wavelet based method, and/or Gaussian smooth method, in order to reduce the artifacts generated by these methods and improve the quality of correction. The implementation of image extrapolation in accordance with a specific embodiment can utilize closest point method. The subject method can also use adaptive smoothing for image intensity correction. In an embodiment, the use of gradient weighted smoothing method can reduce, or eliminate, over-smoothing of bright spot regions. In a specific embodiment, the subject method can utilize gradient weighted partial differential equation (PDE) smoothing.

Abstract: The subject invention pertains to a method of image intensity correction. The subject invention can utilize extrapolation for image intensity correction. The use of extrapolation can reduce the artifacts during intensity correction as compared to traditional methods of intensity correction. The extrapolation can be combined with, for example, homomorphic filtering methods, parametric estimation techniques, wavelet based method, and/or Gaussian smooth method, in order to reduce the artifacts generated by these methods and improve the quality of correction. The implementation of image extrapolation in accordance with a specific embodiment can utilize closest point method. The subject method can also use adaptive smoothing for image intensity correction. In an embodiment, the use of gradient weighted smoothing method can reduce, or eliminate, over-smoothing of bright spot regions. In a specific embodiment, the subject method can utilize gradient weighted partial differential equation (PDE) smoothing.