Abstract: An identity certificate may be issued to a blockchain node. The issuance may include issuing a first identity certificate to a first terminal and receiving a second identity certificate issuance request that is from the first terminal. A second identity certificate may be issued to the first terminal, and a third identity certificate issuance request is received from the second terminal. A third identity certificate is issued to the second terminal, so that the second terminal forwards the third identity certificate to the third terminal.

Abstract: Disclosed are methods and compositions for treating cell proliferative diseases and disorders such as cancers. Particularly disclosed are methods and composition for treating cancers such as glioblastoma by administering a therapeutic agent that inhibits the biological activity of the autophagy related 4B cysteine peptidase (ATG4B) protein in conjunction with additional therapeutic agents or treatments.

Abstract: Implementations of a clamp finger may include a first portion including at least one tip configured to clamp a substrate against an anvil during a bonding operation; and a second portion including a first opening therethrough configured to permit coupling of the second portion with a clamping bridge. The first portion may be slidably coupled with the second portion through a rail and the first portion may include an opening therethrough configured to receive a screw that fixedly couples the at least one tip of the first portion at a desired position relative to the second portion.

Abstract: Disclosed is a composition comprising dichloroacetic acid, a process for preparing the same and a use thereof. It has been discovered that the novel impurity is glyoxylic acid, and glyoxylic acid in dichloroacetic acid can be detected and its concentration accurately measured, by ion chromatography method.

Abstract: Disclosed are a chip power consumption analyzer and an analyzation method thereof. The analyzation method includes the following. Design information of a circuit is received. A plurality of clock arriving times of a plurality of circuit cells in the circuit are calculated based on the design information, and a base cell type is set among a plurality of cell types according to the clock arriving times. Base demand current information of the base cell type is established, and a plurality of demand current information of the circuit cells is obtained. A plurality of demand peak currents of a plurality of bump current sources are predicted according to the demand current information and a plurality of position information of the circuit cells.

Abstract: Disclosed is a composition comprising dichloroacetic acid, a process for preparing the same and a use thereof. It has been discovered that the novel impurity is glyoxylic acid, and glyoxylic acid in dichloroacetic acid can be detected and its concentration accurately measured, by ion chromatography method.

Abstract: Systems and methods are provided that involve processing video to identify a plurality of people in the video; obtaining a plurality of gaze part affinity fields (PAFs) and torso PAFs from the identified plurality of people; determining orthogonal vectors from first vectors derived from the torso PAFs; determining an intersection between second vectors derived from the gaze PAFs and the orthogonal vectors; and changing a viewpoint of the video based on the intersection.

Abstract: Systems and methods are provided that involve processing video to identify a plurality of people in the video; obtaining a plurality of gaze part affinity fields (PAFs) and torso PAFs from the identified plurality of people; determining orthogonal vectors from first vectors derived from the torso PAFs; determining an intersection between second vectors derived from the gaze PAFs and the orthogonal vectors; and changing a viewpoint of the video based on the intersection.

Abstract: A storage memory device includes a field effect transistor including a semiconductor substrate, a first insulating layer that is disposed on the semiconductor substrate, a source and a drain that are formed on the semiconductor substrate and spaced apart from each other, a stacked structure, and a gate. The stacked structure includes a charge trapping layer and a composite element that has a ferroelectric layer and an antiferroelectric layer. The ferroelectric layer is made of a doped hafnium oxide-based material having a predominantly orthorhombic phase and exhibiting a negative capacitance. The antiferroelectric layer is made of a zirconium oxide-based material having a predominantly tetragonal phase.

Abstract: A storage memory device includes a vertical field effect transistor including a semiconductor substrate; a pillar extending upwardly from the substrate and containing a source, a drain, and a channel disposed therebetween; a first insulating layer surrounding the channel; a stacked structure surrounding the first insulating layer; and a gate unit. The stacked structure includes a charge trapping layer and a composite element. The composite element includes a ferroelectric layer made of a doped hafnium oxide-based material that has a predominantly orthorhombic phase and exhibits a negative capacitance; and an antiferroelectric layer made of a zirconium oxide-based material that has a predominantly tetragonal phase.

Abstract: A storage memory device includes a vertical field effect transistor including a semiconductor substrate; a pillar extending upwardly from the substrate and containing a source, a drain, and a channel disposed therebetween; a first insulating layer surrounding the channel; a stacked structure surrounding the first insulating layer; and a gate unit. The stacked structure includes a charge trapping layer and a composite element. The composite element includes a ferroelectric layer made of a doped hafnium oxide-based material that has a predominantly orthorhombic phase and exhibits a negative capacitance; and an antiferroelectric layer made of a zirconium oxide-based material that has a predominantly tetragonal phase.

Abstract: The present disclosure provides a web page processing method. The method includes obtaining web page elements after web page rendering is performed on a to-be-accessed web page; detecting whether an abnormal element exists in the web page elements; generating and displaying an interaction entrance on the to-be-accessed web page if an abnormal element exists in the web page elements; and obtaining a trigger operation on the interaction entrance and filtering out the abnormal element in response to the trigger operation.

Abstract: A flash memory structure and a method of making the same are provided. The flash memory structure comprises a substrate, a source, a drain, a tunnel isolation layer, a ferroelectric-charge-trapping layer, at least one blocking isolation layer and at least one gate. The substrate is made of a semiconductive material. The source is formed on the substrate. The drain is formed on the substrate and spaced apart from the source. The tunnel isolation layer is formed on the substrate. The ferroelectric-charge-trapping layer is formed on the tunnel isolation layer and contains a charge-trapping layer and a ferroelectric negative-capacitance effect layer. The at least one blocking isolation layer is formed on the ferroelectric-charge-trapping layer. The at least one gate is formed on the blocking isolation layer. The ferroelectric negative-capacitance effect layer is made of a material with the ferroelectric negative-capacitance effect.

Abstract: The present disclosure provides a web page processing method. The method includes obtaining web page elements after web page rendering is performed on a to-be-accessed web page; detecting whether an abnormal element exists in the web page elements; generating and displaying an interaction entrance on the to-be-accessed web page if an abnormal element exists in the web page elements; and obtaining a trigger operation on the interaction entrance and filtering out the abnormal element in response to the trigger operation.

Abstract: A flash memory structure and a method of making the same are provided. The flash memory structure comprises a substrate, a source, a drain, a tunnel isolation layer, a ferroelectric-charge-trapping layer, at least one blocking isolation layer and at least one gate. The substrate is made of a semiconductive material. The source is formed on the substrate. The drain is formed on the substrate and spaced apart from the source. The tunnel isolation layer is formed on the substrate. The ferroelectric-charge-trapping layer is formed on the tunnel isolation layer and contains a charge-trapping layer and a ferroelectric negative-capacitance effect layer. The at least one blocking isolation layer is formed on the ferroelectric-charge-trapping layer. The at least one gate is formed on the blocking isolation layer. The ferroelectric negative-capacitance effect layer is made of a material with the ferroelectric negative-capacitance effect.

Abstract: A dynamic random access memory (DRAM) and a manufacturing method thereof are disclosed. A storage cell of the DRAM includes a FINFET and a capacitor. A gate of the FINFET is formed by a metal nitride or a carbonized metal having the effect of stress-induced strain. A gate dielectric of the FINFET and/or a dielectric of the capacitor can be formed by a ferroelectric material having negative capacitance characteristics. A strained-gate engineering is used in the invention achieve effects of (1) increasing ferro-electricity of the dielectric to enhance the operation speed and endurance of the FINFET; and (2) enhancing the ferro negative capacitance effect to improve the sub-threshold swing of the FINFET, so that the switching power and the off-current of the FINFET can be reduced and the charge retention capability of capacitor can be effectively enhanced to improve the operation characteristics of the DRAM.

Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a source and a drain, a p-type nitride layer and a strain gate. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source and the drain are respectively disposed at two sides of the barrier layer. The p-type nitride layer is disposed on the barrier layer. The strain gate is disposed over the p-type nitride layer for tuning a first strain of the channel layer and a second strain of the barrier layer.

Abstract: A three-dimensional non-volatile memory structure including a substrate, a stacked structure, a charge storage pillar, a channel pillar, and a ferroelectric material pillar is provided. The stacked structure is disposed on the substrate and includes a plurality of conductive layers and a plurality of first dielectric layers, and the conductive layers and the first dielectric layers are alternately stacked. The charge storage pillar is disposed in the stacked structure. The channel pillar is disposed inside the charge storage pillar. The ferroelectric material pillar is disposed inside the channel pillar.

Abstract: The disclosure provides a thermoelectric conversion structure and its use in heat dissipation device. The thermoelectric conversion structure includes a thermoelectric element, a first electrode and an electrically conductive heat-blocking layer. The thermoelectric element includes a first end and a second end opposite to each other. The first electrode is located at the first end of the thermoelectric element. The electrically conductive heat-blocking layer is between the thermoelectric element and the first electrode.

Abstract: A semiconductor device for ultra-high voltage (UHV) operation disclosed in the present invention includes a substrate having a normally-on channel, a negative capacitance material layer, an electrode, a source and a drain. The negative capacitance material layer is disposed over the substrate and capable of adjusting the threshold voltage of the semiconductor device so as to transform the normally-on channel into a normally-off channel and change the transistor characteristics of the semiconductor device from a depletion mode to an enhance mode. In addition, the semiconductor device also includes a gate dielectric layer made of high-k material between the negative capacitance material layer, a gate layer between the gate dielectric layer and the negative capacitance material layer and an ion implantation layer in the substrate under the gate. Furthermore, the aforementioned technical features or structures can be formed in a semiconductor device having a gate-recessed structure.