Patents by Inventor Hu Ge
Hu Ge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7495267Abstract: A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.Type: GrantFiled: April 21, 2006Date of Patent: February 24, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lee, Chung-Hu Ge, Chenming Hu
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Patent number: 7453133Abstract: A preferred embodiment of the present invention comprises a dielectric/metal/2nd energy bandgap (Eg) semiconductor/1st Eg substrate structure. In order to reduce the contact resistance, a semiconductor with a lower energy bandgap (2nd Eg) is put in contact with metal. The energy bandgap of the 2nd Eg semiconductor is lower than the energy bandgap of the 1st Eg semiconductor and preferably lower than 1.1eV. In addition, a layer of dielectric may be deposited on the metal. The dielectric layer has built-in stress to compensate for the stress in the metal, 2nd Eg semiconductor and 1st Eg substrate. A process of making the structure is also disclosed.Type: GrantFiled: June 30, 2004Date of Patent: November 18, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lee, Chung-Hu Ge, Chenming Hu
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Patent number: 7342289Abstract: A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate.Type: GrantFiled: August 8, 2003Date of Patent: March 11, 2008Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chien-Chao Huang, Chung-Hu Ge, Wen-Chin Lee, Chenming Hu, Carlos H. Diaz, Fu-Liang Yang
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Patent number: 7321155Abstract: A strained channel transistor and method for forming the same, the strained channel transistor including a semiconductor substrate; a gate dielectric overlying a channel region; a gate electrode overlying the gate dielectric; source drain extension (SDE) regions and source and drain (S/D) regions; wherein a stressed dielectric portion selected from the group consisting of a pair of stressed offset spacers disposed adjacent the gate electrode and a stressed dielectric layer disposed over the gate electrode including the S/D regions is disposed to exert a strain on a channel region.Type: GrantFiled: May 6, 2004Date of Patent: January 22, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hsin Ko, Wen-Chin Lee, Chung-Hu Ge
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Patent number: 7310850Abstract: The present invention is a handheld and highly mobile device with paddle extensions adapted to be comfortably inserted at the same time between a user's toes. The paddle extensions can be moved in an up and down sliding motion for massage or cleaning of inter-toe surfaces. The paddle extensions provide massage in one embodiment and scrubbing or cleansing in another embodiment. In a cleansing embodiment, the invention device incorporates a readily cleaned or disposable glove that form-fits over the paddles. The glove is made of absorbent material with a smooth to coarse outside surface to facilitate cleaning and/or scrubbing.Type: GrantFiled: October 13, 2005Date of Patent: December 25, 2007Inventor: Jack Hu Ge
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Publication number: 20070161206Abstract: A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.Type: ApplicationFiled: October 26, 2006Publication date: July 12, 2007Inventors: Chih-Hsin Ko, Yee-Chia Yeo, Wen-Chin Lee, Chung-Hu Ge
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Publication number: 20070099402Abstract: A reliable semiconductor structure and its fabrication method. Active regions and/or scribe lines on a semiconductor substrate are configured along a crack resistant crystalline direction. Thermal cracking due to the abrupt temperature ramp of rapid thermal processing can be avoided.Type: ApplicationFiled: December 20, 2006Publication date: May 3, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Horng-Huei Tseng, Chung-Hu Ge, Chao-Hsiung Wang
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Patent number: 7208754Abstract: A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at least part of the first trench, and the second trench is at least partially filled with an insulating material.Type: GrantFiled: April 26, 2005Date of Patent: April 24, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hu Ge, Wen-Chin Lee, Chenming Hu
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Patent number: 7183593Abstract: A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.Type: GrantFiled: December 24, 2003Date of Patent: February 27, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yee-Chia Yeo, Wen-Chin Lee, Chih-Hsin Ko, Chung-Hu Ge, Chun-Chieh Lin, Chenming Hu
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Publication number: 20060138557Abstract: A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.Type: ApplicationFiled: February 17, 2006Publication date: June 29, 2006Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chao Huang, Chao-Hsing Wang, Chung-Hu Ge, Chenming Hu
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Patent number: 7045836Abstract: A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.Type: GrantFiled: September 8, 2003Date of Patent: May 16, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lee, Chung-Hu Ge, Chenming Hu
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Patent number: 7029994Abstract: A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.Type: GrantFiled: March 18, 2005Date of Patent: April 18, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hu Ge, Chao-Hsiung Wang, Chien-Chao Huang, Wen-Chin Lee, Chenming Hu
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Patent number: 7022561Abstract: A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.Type: GrantFiled: December 2, 2002Date of Patent: April 4, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chao Huang, Chao-Hsing Wang, Chung-Hu Ge, Chenming Hu
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Publication number: 20050285140Abstract: A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.Type: ApplicationFiled: June 23, 2004Publication date: December 29, 2005Inventors: Chih-Hsin Ko, Yee-Chia Yeo, Wen-Chin Lee, Chung-Hu Ge
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Patent number: 6974755Abstract: A semiconductor isolation trench includes a substrate and a trench formed therein. The trench is lined with a nitrogen-containing liner and filled with a dielectric material. The nitrogen-containing liner preferably contacts the active region of a device, such as a transistor, located adjacent to the trench.Type: GrantFiled: October 16, 2003Date of Patent: December 13, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsin Ko, Yee-Chia Yeo, Chung-Hu Ge, Wen-Chin Lee
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Publication number: 20050247986Abstract: A strained channel transistor and method for forming the the strained channel transistor including a semiconductor rate; a gate dielectric overlying a channel region; a gate rode overlying the gate dielectric; source drain extension regions and source and drain (S/D) regions; wherein a sed dielectric portion selected from the group consisting of r of stressed offset spacers disposed adjacent the gate rode and a stressed dielectric layer disposed over the gate rode including the S/D regions is disposed to exert a strain channel region.Type: ApplicationFiled: May 6, 2004Publication date: November 10, 2005Inventors: Chih-Hsin Ko, Wen-Chin Lee, Chung-Hu Ge
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Publication number: 20050236616Abstract: A reliable semiconductor structure and its fabrication method. Active regions and/or scribe lines on a semiconductor substrate are configured along a crack resistant crystalline direction. Thermal cracking due to the abrupt temperature ramp of rapid thermal processing can be avoided.Type: ApplicationFiled: April 26, 2004Publication date: October 27, 2005Inventors: Horng-Huei Tseng, Chung-Hu Ge, Chao-Hsiung Wang
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Patent number: 6924181Abstract: A strained silicon layer fabrication and a method for fabrication thereof employ a strained insulator material layer formed over a strained silicon layer in turn formed upon a strained silicon-germanium alloy material layer which is formed upon a relaxed material substrate. The strained insulator material layer provides increased fabrication options which provide for enhanced fabrication efficiency when fabricating the strained silicon layer fabrication.Type: GrantFiled: February 13, 2003Date of Patent: August 2, 2005Assignee: Taiwan SEmiconductor Manufacturing Co., LtdInventors: Chien-Chao Huang, Chao-Hsiung Wang, Chung-Hu Ge, Wen-Chin Lee, Chen Ming Hu
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Patent number: 6902965Abstract: A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at lease part of the first trench, and the second trench is at least partially filled with an insulating material.Type: GrantFiled: October 31, 2003Date of Patent: June 7, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hu Ge, Wen-Chin Lee, Chenming Hu
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Publication number: 20050116360Abstract: A complementary FET and a method of manufacture is provided. The complementary FET utilizes a substrate having a surface layer with a <100> crystal orientation. Tensile stress, which increases performance of the NMOS FETs, is added by silicided source/drain regions, tensile-stress film, shallow trench isolations, inter-layer dielectric, or the like.Type: ApplicationFiled: July 21, 2004Publication date: June 2, 2005Inventors: Chien-Chao Huang, Fu-Liang Yang, Mickey Ken, Chenming Hu, Chung-Hu Ge, Wen-Chin Lee, Chih-Hsin Ko