Isolation structure for strained channel transistors
A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.
The present disclosure relates generally to the field of semiconductor devices, and more particularly to strained channel transistors with enhanced performance using improved isolation regions and the method for making same.
BACKGROUNDSize reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET), including reduction of the gate length and gate oxide thickness, has enabled the continued improvement in speed performance, density, and cost per unit function of integrated circuits over the past few decades. To enhance transistor performance further, strain may be introduced in the transistor channel for improving carrier mobility. Therefore, strain-induced mobility enhancement is another way to improve transistor performance in addition to device scaling. Several existing approaches of introducing strain in the transistor channel region have been proposed.
There are several existing approaches of introducing strain in the transistor channel region to enhance further transistor performance. In one conventional approach, a relaxed silicon germanium (SiGe) buffer layer 102 is provided beneath the channel region, as shown in
In a conventional shallow trench isolation process 200, as shown in
What is needed is an improved isolation structure for strained channel transistors and the method for making same.
SUMMARY OF INVENTIONIn view of the foregoing, the present disclosure provides a system and method for forming an improved isolation structure for strained channel transistors.
In one example, an isolation structure is formed comprising a trench filled with a silicon oxide liner, a nitrogen-containing liner, and a gap filler. In another example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region. The nitrogen-containing liner minimizes confined volume expansion and reduces compressive stress in the surrounding active region.
The present disclosure provide isolation structures with reduced compressive strain contribution and reduced thermal budget in a tensile strained silicon substrate. Another object of the present disclosure is to teach a method of engineering the strain in the channel of the tensile strained transistor by engineering the isolation structure to improve transistor performance.
These and other aspects and advantages will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the disclosure.
BRIEF DESCRIPTION OF DRAWINGSThe present disclosure will be more clearly understood after reference to the following detailed description of preferred embodiments read in conjunction with the drawings, wherein:
FIGS. 1(a)-(b) illustrate the cross-section of a conventional strained silicon transistor with a relaxed SiGe and the illustration of the origin of strain in the Si/SiGe hetero-structure, respectively.
FIGS. 3(a)-(b) illustrate a novel low-stress isolation structure for the strained silicon transistor according to one example of the present disclosure.
FIGS. 4(a)-(e) illustrate a first method of manufacturing a novel low-stress isolation structure for the strained silicon transistor according to another example of the present disclosure.
FIGS. 5(a)-(e) illustrate a second method of manufacturing a novel low-stress isolation structure for the strained silicon transistor according to another example of the present disclosure.
FIGS. 6(a)-(e) illustrate a third method of manufacturing a novel low-stress isolation structure for the strained silicon transistor according to another example of the present disclosure.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTSAs illustrated below, the structure of and methods are disclosed below for the manufacture of an improved isolation structure with reduced compression strain contribution to the channel region and/or reduced thermal budget. Several embodiments are shown as illustrated examples.
First Embodiment
FIGS. 4(a)-(e) illustrate a first method embodiment of the present disclosure, describing a process flow for forming strained silicon transistors with reduced thermal budget and reduced compressive strain contribution by the isolation structure to the channel region. The isolation structure 400 preferably comprises a nitrogen-containing liner 402 in direct contact with the trench sidewall surface 404. The nitrogen-containing liner 402 can be a single silicon nitride layer or a silicon oxynitride layer 406. The nitrogen content of the nitrogen-containing liner 402 may be in the range of 5 to 60 percent (%) by atomic percentage. A substrate comprising a strained silicon layer 408 overlying a relaxed silicon-germanium (SiGe) layer 410 is used as the starting material. Such a substrate may further comprise a grade SiGe buffer layer 412, and may further comprise a silicon substrate 414 underlying the grade SiGe buffer layer 412. A first patterned mask is formed on the substrate, and the trenches 416 are etched into the substrate, as shown in
The cross-section in
The cross-section in
FIGS. 5(a)-(e) illustrate a second method embodiment of the present disclosure, describing a process flow for forming strained silicon transistors with reduced thermal budget and compressive strain contribution by the isolation structure to the channel region. The isolation structure 500 preferably comprises a nitrogen-containing liner 502 overlying a silicon oxide liner 504. In this method embodiment, the silicon oxide liner 504 is formed by chemical vapor deposition, preferably plasma-enhanced chemical vapor deposition (PECVD). The silicon oxide liner 504 is in direct contact with the trench sidewall surface 506. A substrate comprising a strained silicon layer 508 overlying a relaxed silicon-germanium (SiGe) layer 510 is used as the starting material. The starting substrate may further comprise a silicon substrate 512 underlying a graded SiGe buffer layer 514. A first patterned mask is formed on the substrate, and trenches 516 are etched into the substrate, as illustrated in
The cross-section illustrated in
A planarization step, preferably using a chemical mechanical polishing process, is performed. The resulting cross-section is illustrated in
FIGS. 6(a)-(e) illustrate a third method embodiment of the present disclosure, describing a process flow for forming strained silicon transistors with reduced thermal budget and compressive strain contribution by the isolation structure to the channel region. The isolation structure 600 comprises a nitrogen-containing liner 602 overlying a silicon oxide liner 604. The third method embodiment differs from the second method embodiment of the present disclosure in that the silicon oxide liner 604 of the third method embodiment is formed by a thermal oxidation process. The thermally grown silicon oxide liner 604 is in direct contact with the trench sidewall surface 606. Since the growth of the thermal oxide results in rounded corners, the corner rounding process is optional. A substrate comprising a strained silicon layer 608 overlying a relaxed silicon-germanium (SiGe) layer 610 is used as the starting material. A first patterned mask is formed on the substrate, and trenches 612 are etched into the substrate, as illustrated in
The cross-section illustrated in
A planarization step, preferably using a chemical mechanical polishing process, is performed. The resulting cross-section is illustrated in
The above disclosure provides many different embodiments, or examples, for implementing different features of the present disclosure. Specific examples of components, and processes are described to help clarify the present disclosure. These are, of course, merely examples and are not intended to limit the present disclosure from that described in the claims. For example, while a shallow trench isolation is illustrated, it is understood that the present disclosure may be extended to other isolation structures, which are improvements of the shallow trench isolation structure. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense.
While the present disclosure has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure, as set forth in the following claims.
Claims
1. A strained channel transistor with at least one isolation structure, the transistor being formed on a semiconductor substrate comprising a strained silicon layer overlying a tensile strain forming buffer layer, the isolation structure comprising:
- an active region formed in the semiconductor substrate; and
- at least one nitrogen-containing liner isolation region next to the active region.
2. The transistor according to claim 1, wherein the isolation region is a shallow trench isolation region with a trench depth in the range of 2000 to 6000 angstroms.
3. The transistor according to claim 1, wherein the nitrogen-containing liner has a thickness in the range of 10 to 500 angstroms.
4. The transistor according to claim 1, wherein a channel region is formed in the strained silicon layer of the active region with a source or drain region formed between the channel region and the isolation region.
5. The transistor according to claim 1, wherein the tensile strain forming buffer layer is a relaxed silicon-germanium layer.
6. The transistor according to claim 5, wherein the substrate further comprises a graded silicon-germanium buffer layer underlying the relaxed silicon-germanium layer, the graded silicon-germanium buffer layer overlying a silicon substrate.
7. The transistor according to claim 1, wherein the isolation region further comprises an oxide liner underlying the nitrogen-containing liner.
8. The transistor according to claim 1, wherein the isolation region includes a gap filler material.
9. The transistor according to claim 1, wherein the nitrogen-containing liner comprises at least one of silicon nitride, silicon oxynitride, or nitrogen-doped silicon oxide.
10. The transistor according to claim 1, wherein the nitrogen-containing liner has a nitrogen content of 5 to 60 percent (%).
11. The transistor according to claim 1, wherein a in-plane tensile strain of a channel region of the active region is between 0.1% to 2%.
12. A method of forming an isolation structure for strained channel transistors comprising:
- providing a semiconductor substrate comprising a strained silicon layer overlying a strain forming buffer layer;
- forming a trench in the semiconductor substrate;
- forming a nitrogen-containing liner in the trench; and
- filling the trench with a gap filler material,
- wherein the nitrogen-containing liner reduces a compressive strain asserted on the strained silicon layer by the gap filler material contained therein.
13. The method according to claim 12, wherein the nitrogen-containing liner is comprised of silicon nitride or silicon oxynitride.
14. The method according to claim 12, wherein the nitrogen-containing liner has a nitrogen content of 5 to 60 percent (%).
15. The method according to claim 12, wherein the nitrogen-containing liner has a thickness in the range of 10 to 500 angstroms.
16. The method according to claim 12, further comprising the step of, after the step of forming the trench, of forming a silicon oxide liner underlying the nitrogen-containing liner.
17. The method according to claim 16, wherein the step of forming the silicon oxide liner is a thermal oxidation step or a chemical vapor deposition step.
18. The method according to claim 12, further comprising the step, after the step of forming the trench, of performing a corner rounding process step.
19. The method according to claim 18, wherein the corner rounding process step is an anneal at a temperature in the range of 700 to 950 degrees Celsius in a gaseous ambient, the gaseous ambient.
20. The method according to claim 18, further comprising a step, after the step of corner rounding, of forming a silicon oxide liner.
21. The method according to claim 18, wherein the step of forming the silicon oxide liner is a thermal oxidation step or a chemical vapor deposition step.
22. The method according to claim 18, wherein forming the trench in the semiconductor substrate further includes forming a pull back of the opening of the trench.
23. The method according to claim 22, wherein the pull back is in the range of 50 to 1000 angstroms.
24. The method according to claim 22, wherein the pull back is formed by a chemical treatment with a wet etch process in hot acid at a temperature in the range of 150 to 180 degrees Celsius.
25. The method according to claim 24, wherein the chemical treatment further includes a wet etch process in dilute hydrochloric acid.
Type: Application
Filed: Jun 23, 2004
Publication Date: Dec 29, 2005
Inventors: Chih-Hsin Ko (Fongstan City), Yee-Chia Yeo (Singapore), Wen-Chin Lee (Hsinchu), Chung-Hu Ge (Taipei)
Application Number: 10/875,141