Abstract: A circuit board structure and a manufacturing method thereof. Circuit board structure includes first circuit board, second circuit board, conductive coil, magnetic body and molding compound. First circuit board has first side surface and first cavity located on first side surface. Second circuit board has second side surface facing first side surface and being spaced apart from first side surface. Conductive coil is in a spiral shape and includes first coil pattern and second coil pattern. First coil pattern is disposed in first circuit board. Second coil pattern is disposed in second circuit board. First coil pattern is electrically connected to second coil pattern. Magnetic body is filled in first cavity of first circuit board. Conductive coil surrounds at least a part of magnetic body. Molding compound is filled in a gap between first side surface and second side surface.

Abstract: Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.

Abstract: The present disclosure, in some embodiments, relates to a capacitor structure. The capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A lower electrode is arranged along sidewalls and an upper surface of the lower dielectric structure, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is arranged along outermost sidewalls of the upper electrode. The spacer includes a first upper surface arranged along a first side of the upper electrode and a second upper surface arranged along an opposing second side of the upper electrode. The first upper surface has a different width than the second upper surface.

Abstract: A heating platform for heating a wafer is provided. The heating platform includes a support carrier, a detection module and a first heating module. The wafer is supported by the support carrier. The detection module is configured to monitor a surface condition of the wafer supported by the support carrier. The first heating module is disposed at a side of the support carrier. The first heating module includes a plurality of heating units electrically connected to the detection module, and the heating units is arranged in an array. A thermal treatment and a manufacturing method are further provided.

Abstract: Embodiments include a device. The device includes an interposer, a package substrate, and conductive connectors bonding the package substrate to the interposer. Each of the conductive connectors have convex sidewalls. A first subset of the conductive connectors are disposed in a center of the package substrate in a top-down view. A second subset of the conductive connectors are disposed in an edge/corner of the package substrate in the top-down view. Each of the second subset of the conductive connectors have a greater height than each of the first subset of the conductive connectors.

Abstract: The disclosure relates to compounds of Formula (I) as allosteric chromenone inhibitors of phosphoinositide 3-kinase (PI3K) useful in the treatment of diseases or disorders associated with PI3K modulation, Formula (I): or pharmaceutically acceptable salts thereof wherein R, R1, R2, R3, R4, R5, R6, R7, and R8, are as defined herein. The disclosure also relates to methods of making and using compounds of Formula (I) or pharmaceutically acceptable salts thereof.

Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

Abstract: The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.

Abstract: A manufacturing method of group III-V semiconductor package is provided. The manufacturing method includes the following steps. A wafer comprising group III-V semiconductor dies therein is provided. A chip probing (CP) process is performed to the wafer to determine reliabilities of the group III-V semiconductor dies, wherein the CP process comprises performing a multi-step breakdown voltage testing process to the group III-V semiconductor dies to obtain a first portion of dies of the group III-V semiconductor dies with breakdown voltages to be smaller than a predetermined breakdown voltage. A singulation process is performed to separate the group III-V semiconductor dies from the wafer. A package process is performed to form group III-V semiconductor packages including the group III-V semiconductor dies. A final testing process is performed on the group III-V semiconductor packages.

Abstract: A synthesis and an application of a phosphatase degrader are provided. The phosphatase degrader is a compound represented by formula I, or a salt thereof, or a deuterated compound thereof, or a stereoisomer thereof, or a solvate thereof, or a hydrate thereof, or a prodrug thereof. The compound can be used as a phosphatase degrader, especially as an SHP2 protein degrader, can treat malignant diseases such as tumors, and has good application prospects.

Abstract: The present invention provides a flow control switch including a pipeline structure, a rotating structure, a position-limiting structure and a knob structure. The pipeline structure includes a tubular body and a ball body rotatably disposed in the tubular body. The rotating structure includes a rotatable element connected to the ball body for driving the ball body to rotate. The position-limiting structure is disposed on the tubular body. The knob structure is liftably disposed on the rotating structure for cooperating with the rotatable element. The position-limiting structure has a first and a second position-limiting groove. The knob structure includes a knob body liftably disposed on the rotatable element and a position-limiting element detachably disposed on the knob body. The position-limiting element is optionally disposed in one of the first and the second position-limiting groove, so as to limit a rotation of the rotatable element relative to the position-limiting structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: This application relates to a sampling component, a battery module, a battery pack, and a device. The sampling component includes: a circuit board, including a signal collecting portion and an insulation film connected to the signal collecting portion; and a connecting part, including a body portion and a connecting portion, where the body portion is connected to the connecting portion, and the connecting portion is electrically connected to the signal collecting portion. In a height direction, the connecting portion includes a first connecting section and a second connecting section. The first connecting section is connected to the second connecting section. In the height direction, at least a part of the signal collecting portion is located between the first connecting section and the second connecting section.

Abstract: Provided are an antibacterial coating and a preparation method and use thereof. The preparation method includes: dissolving catecholamine, bacitracin, and a metal ion in a tris(hydroxymethyl)aminomethane solution (Tris solution) to obtain a dissolved mixture, subjecting the dissolved mixture to reaction on a titanium sheet for 24 h at ambient temperature under an aerobic environment, then subjecting a surface of the titanium sheet to ultrasonic cleaning to remove a precipitate thereon, and conducting blow-drying to obtain the antibacterial coating.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: A package structure and a formation method are provided. The method includes forming a capacitor element over a first chip structure and forming a dielectric layer over the capacitor element. The method also includes forming a conductive bonding structure in the dielectric layer. A top surface of the conductive bonding structure is substantially coplanar with a top surface of the dielectric layer. The conductive bonding structure penetrates through the capacitor element and is electrically connected to the capacitor element. The method further includes bonding a second chip structure to the dielectric layer and the conductive bonding structure through dielectric-to-dielectric bonding and metal-to-metal bonding.

Abstract: A side window encapsulation includes: a light group assembly and an encapsulation frame. The encapsulation frame defines a mounting opening for receiving glass. The side surface of the encapsulation frame facing away from the interior of the vehicle is an outer side surface. A mounting groove is formed on the outer side surface of the encapsulation frame. The light group assembly is detachably mounted in the mounting groove. An insertion part and an engaging part are respectively provided on two opposite side walls of the mounting groove. An insertion-fitting part is provided on the light group assembly and at positions corresponding to the insertion part. The insertion-fitting part is detachably inserted in the insertion part. A fastening member is provided on the light group assembly and at positions corresponding to the engaging part. The fastening member is detachably engaged with the engaging part.

Abstract: A circuit board structure including a first circuit board, a second circuit board, a conductive coil and a first molding compound and a manufacturing method thereof. The first circuit board has a first side surface. The second circuit board has a second side surface facing the first side surface and being spaced apart from the first side surface. The conductive coil is in a spiral shape and includes a first coil pattern and a second coil pattern. The first coil pattern is disposed in the first circuit board. The second coil pattern is disposed in the second circuit board. The first coil pattern is electrically connected to the second coil pattern. The first molding compound is magnetic and filled in a gap located between the first side surface and the second side surface. The conductive coil surrounds at least a part of the first molding compound.

Abstract: According to one embodiment, a method, computer system, and computer program product for head-driven, self-captured photography is provided. The embodiment may include detecting a trigger event performed by a user while the user is interacting with a virtual environment. The embodiment may also include displaying a virtual camera within the virtual environment. The embodiment may further include modifying a location, a distance, and an orientation of the virtual camera in relation to the user based on a plurality of facial movement trigger events by the user. The embodiment may also include capturing one or more images using the virtual camera at the location, the distance, and the orientation based on a facial movement trigger event within the plurality of facial movement trigger events.

Abstract: The present disclosure provides a centrifugal fan impeller, a fan, and an air conditioning system, which solve the technical problems of a small air volume and large noise of a centrifugal fan, low efficiency of a fan, and a relatively concentrated airflow. The centrifugal fan impeller includes blades and a fixing disk, the blades being forward-curved structures and fixed to the fixing disk, wherein in a height direction of the blades, widths of all or part of the blades progressively increase from a suction port to the fixing disk, so that the suction port of the fan impeller is a tapering trumpet-like structure. The fan includes a centrifugal fan impeller, and a volute, which is inclined on two sides. The air conditioning system includes a fan.