Patents by Inventor Hua Chen

Hua Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387613
    Abstract: The present disclosure, in some embodiments, relates to a capacitor structure. The capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A lower electrode is arranged along sidewalls and an upper surface of the lower dielectric structure, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is arranged along outermost sidewalls of the upper electrode. The spacer includes a first upper surface arranged along a first side of the upper electrode and a second upper surface arranged along an opposing second side of the upper electrode. The first upper surface has a different width than the second upper surface.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Publication number: 20240386744
    Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Chih Huang, Chih-Hua Chen, Yu-Jen Cheng, Chih-Wei Lin, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240389232
    Abstract: A circuit board structure and a manufacturing method thereof. Circuit board structure includes first circuit board, second circuit board, conductive coil, magnetic body and molding compound. First circuit board has first side surface and first cavity located on first side surface. Second circuit board has second side surface facing first side surface and being spaced apart from first side surface. Conductive coil is in a spiral shape and includes first coil pattern and second coil pattern. First coil pattern is disposed in first circuit board. Second coil pattern is disposed in second circuit board. First coil pattern is electrically connected to second coil pattern. Magnetic body is filled in first cavity of first circuit board. Conductive coil surrounds at least a part of magnetic body. Molding compound is filled in a gap between first side surface and second side surface.
    Type: Application
    Filed: July 11, 2023
    Publication date: November 21, 2024
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Chun Hung KUO, Kuo-Ching CHEN, Yu-Cheng HUANG, Yu-Hua CHEN
  • Publication number: 20240387498
    Abstract: Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Publication number: 20240387645
    Abstract: The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Wei-Yen Woon, Cheng-Ming Lin, Han-Yu Lin, Szu-Hua Chen
  • Publication number: 20240375577
    Abstract: A side window encapsulation includes: a light group assembly and an encapsulation frame. The encapsulation frame defines a mounting opening for receiving glass. The side surface of the encapsulation frame facing away from the interior of the vehicle is an outer side surface. A mounting groove is formed on the outer side surface of the encapsulation frame. The light group assembly is detachably mounted in the mounting groove. An insertion part and an engaging part are respectively provided on two opposite side walls of the mounting groove. An insertion-fitting part is provided on the light group assembly and at positions corresponding to the insertion part. The insertion-fitting part is detachably inserted in the insertion part. A fastening member is provided on the light group assembly and at positions corresponding to the engaging part. The fastening member is detachably engaged with the engaging part.
    Type: Application
    Filed: September 21, 2022
    Publication date: November 14, 2024
    Inventors: Dong ZENG, Hua CHEN, Ke ZHANG, Xiuyong OU, Changhe YU, Qiming LIN, Ronglin CHEN
  • Publication number: 20240381533
    Abstract: A circuit board structure including a first circuit board, a second circuit board, a conductive coil and a first molding compound and a manufacturing method thereof. The first circuit board has a first side surface. The second circuit board has a second side surface facing the first side surface and being spaced apart from the first side surface. The conductive coil is in a spiral shape and includes a first coil pattern and a second coil pattern. The first coil pattern is disposed in the first circuit board. The second coil pattern is disposed in the second circuit board. The first coil pattern is electrically connected to the second coil pattern. The first molding compound is magnetic and filled in a gap located between the first side surface and the second side surface. The conductive coil surrounds at least a part of the first molding compound.
    Type: Application
    Filed: June 2, 2023
    Publication date: November 14, 2024
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Chun Hung KUO, Kuo-Ching CHEN, Yu-Cheng HUANG, Yu-Hua CHEN
  • Publication number: 20240369179
    Abstract: A composite fixed bracket includes a device-end bracket, a fixed-end bracket and an auxiliary fixing bracket. The device-end bracket has first rotating-connecting parts and device connection parts connecting an electronic device. The fixed-end bracket has second rotating-connecting parts, first sliding-connecting parts and hole parts. The first and the second rotating-connecting parts are relatively rotated to fit and connect to each other for fixing the fixed-end and device-end brackets. The fixed-end bracket is located between the device-end bracket and the auxiliary fixing bracket. The auxiliary fixing bracket includes two fixing units, and each fixing unit includes two second sliding-connecting parts, an engaging part and a ring-fixing part. The second sliding-connecting parts are connected to the first sliding-connecting parts respectively, so the fixing units are slidably connected to the fixed-end bracket.
    Type: Application
    Filed: February 20, 2024
    Publication date: November 7, 2024
    Inventor: Chin-Hua CHEN
  • Patent number: 12136570
    Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: November 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Wei-Yen Woon, Cheng-Ming Lin, Han-Yu Lin, Szu-Hua Chen, Jhih-Rong Huang, Tzer-Min Shen
  • Patent number: 12134274
    Abstract: An example device may comprise a molded structure and a dependent device coupled to the molded structure. The molded structure comprises thermo-electric traces and channels. The channels are between ten ?m and two hundred ?m, or less in one dimension. The dependent device comprises apertures corresponding to the channels and through which fluids, electromagnetic radiation, or a combination thereof is to travel. The dependent device also comprises contacts corresponding to the thermo-electric traces of the molded structure.
    Type: Grant
    Filed: August 23, 2023
    Date of Patent: November 5, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chien-Hua Chen, Michael W. Cumbie, Michael G. Groh
  • Patent number: 12136686
    Abstract: A diode array includes a substrate and a plurality of light emitting diodes disposed on the substrate and arranged in an array. Each of the light emitting diodes includes a stack of functional layers includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer located between the first semiconductor layer and the second semiconductor layer. At least one of the light emitting diodes includes a first current limiting region covering at least a portion of the first semiconductor layer, the light emitting layer or the second semiconductor layer; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the second semiconductor layer, wherein the first electrode and the second electrode are disposed at the same side of the first semiconductor layer.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: November 5, 2024
    Assignee: VISIONLABS CORPORATION
    Inventors: Hung-Cheng Lin, Hung-Kuang Hsu, Hua-Chen Hsu
  • Publication number: 20240363421
    Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Yu LIN, Szu-Hua Chen, Kuan-Kan Hu, Kenichi Sano, Po-Cheng Wang, Wei-Yen Woon, Pinyen Lin, Che Chi Shih
  • Publication number: 20240363464
    Abstract: A package structure is provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The through via extends through the encapsulant and the first redistribution line structure and connecting the second RDL structure. The through via is laterally separated from the redistribution layer by the dielectric layer therebetween.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
  • Publication number: 20240359341
    Abstract: A modular gripper is disclosed and includes a main fixing plate, a driving module, two screw rods, two extension plates, two extension screws and two nuts. The two screw rods are arranged concentrically in the first direction, connected to the driving module, and driven by the driving module to rotate. The two extension plates are detachably docked to two sides of the main fixing plate through connection elements. The two extension screws are connected to the two screw rods, respectively. Threads of the two extension screws are continuously connected with threads of the two screw rods. The two nuts are sleeved on the two screw rods, respectively. When the two screw rods and the two extension screws are driven by the driving module to rotate synchronously, the two nuts are allowed to displace relative to the two screw rods and the two extension screws, to achieve a clamping operation.
    Type: Application
    Filed: August 25, 2023
    Publication date: October 31, 2024
    Inventors: Hsin-Hua Chen, Tsao-Hsiang Wang
  • Publication number: 20240363095
    Abstract: Managing noise during an online conference session includes obtaining audio data from an endpoint participating in an online conference session. The audio data is derived from audio captured at the endpoint that includes musical sounds. The audio data is processed to identify a portion of the audio data in which a decibel level of the musical sounds is stable for a period of time. Non-musical noise present, if any, in the audio data with the musical sounds is identified and the non-musical noise is attenuated from the audio data to generate noise-reduced musical audio data. The noise-reduced musical audio data is transmitted for play out at one or more other endpoints participating in the online conference session.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Bjørn Winsvold, Eric Yi-hua Chen, Wei-Lien Hsu, Pi-Hsin Liu
  • Publication number: 20240361609
    Abstract: Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×1019 per cubic centimeter (cm?3) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Hsin-Yu CHEN, Chun-Peng LI, Chia-Chun HUNG, Ching-Hsiang HU, Wei-Ding WU, Jui-Chun WENG, Ji-Hong CHIANG, Yen Chiang LIU, Jiun-Jie CHIOU, Li-Yang TU, Jia-Syuan LI, You-Cheng JHANG, Shin-Hua CHEN, Lavanya SANAGAVARAPU, Han-Zong PAN, Hsi-Cheng HSU
  • Publication number: 20240359340
    Abstract: A gripper structure is disclosed and includes a screw-rod main body, a first rotatory nut, a second rotatory nut, a first driving module, a second driving module, a first clamping element and a second clamping element. The first rotatory nut and the second rotatory nut are disposed on two sides of the screw-rod main extended along a first direction body, respectively, and bilaterally symmetrical to each other. The first driving module and the second driving module are configured to drive the first rotatory nut and the second rotatory nut to rotate, respectively. The first rotatory nut and the second rotatory nut are allowed to pass through a midline of the screw-rod main body. When the first driving module drives the first rotatory nut or/and the second driving module drives the second rotatory nut, the first clamping element and the second clamping element are relatively displaced in the first direction to achieve a clamping operation.
    Type: Application
    Filed: August 25, 2023
    Publication date: October 31, 2024
    Inventors: Hsin-Hua Chen, Shang-Wei Yang, Hsin-Hsien Wu
  • Publication number: 20240357068
    Abstract: The invention relates to the technical field of camera, in particular, to a hand-held binocular fisheye 3D VR camera, which includes a housing and a lens assembly mounted on the housing. A bottom surface inside the housing is mounted with an MIC board, and a main bracket is mounted inside the housing. A rear surface of the main bracket is provided with a structural port plate, a sensor body and a sensor board bracket. A front surface of the main bracket is mounted with a cooling bracket and a main board, and one end of the rear surface of the main bracket is mounted with a speaker. The invention is provided with the MIC board and the speaker, supporting three recording modes of photographing, video recording and live broadcast.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 24, 2024
    Applicant: CALF TECHNOLOGY PTE.LTD.
    Inventor: Hua CHEN
  • Patent number: 12125193
    Abstract: A method of detecting defects revealed in images of finished products includes importing flawless images into an autoencoder for model training and obtaining reconstructed images from them. The reconstructed images are compared with the flawless images to obtain groups of test errors. An error threshold is selected from the groups of the test errors according to preset rules. In practice, obtaining an image to be tested, and a reconstructed image to be tested, and an error to be tested; determining detection of the image to be tested according to the error and the error threshold; and importing the image into a classifier for defect classification if the image is found to reveal a defect. An electronic device and a non-volatile storage medium for performing the above-described method, are also disclosed.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: October 22, 2024
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: I-Hua Chen, Tung-Tso Tsai, Chin-Pin Kuo, Tzu-Chen Lin
  • Patent number: 12119946
    Abstract: A power over Ethernet (PoE) power supplying method where power sourcing equipment (PSE) and a powered device exchange link layer discovery protocol data units (LLDPDUs). Each of the LLDPDUs includes two power values. Each of the power values indicates requested or allocated power for one of two sets of cable pairs of the Ethernet twisted pair connecting the PSE and the powered device. Accordingly, the supplied powers to the powered device at sets of cable pairs are independent from each other.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: October 15, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yan Zhuang, Shiyong Fu, Hua Chen, Xiuju Liang, Jincan Cao, Rui Hua