Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Abstract: A system and method for authenticating a user via a single voice audio input is disclosed. The method includes obtaining voice audio from a user, converting the voice audio to text, comparing at least a portion of the text to a database, determining whether a user profile exists in the database based on the comparing, the user profile including a voiceprint, in response to determining that the user profile exists in the database, analyzing the voice audio against the voiceprint of the user profile; and authenticating the user based on the voice audio substantially matching the voiceprint of the user profile.

Abstract: An antenna module includes an antenna box and a first connection wire. The antenna box can include a first antenna, a second antenna, a first connection terminal, a second connection terminal and a housing. The first and second antennas are located in the housing and the housing has a first opening collectively exposing a portion of the first connection terminal and a portion of the second connection terminal. Each of the first and second antennas is adapted to receive or transmit wireless signals according to one of a plurality of wireless communication standards and the first and second antennas are electrically connected to the first and second connection terminals, respectively. The wireless communication standards can be different from each other.

Abstract: A battery device comprises a case, a core pack, a signal unit and a non-volatile memory, wherein the core pack, the signal unit and the non-volatile memory are disposed in the case. The case has a first transmission terminal and a second transmission terminal. The signal unit is electrically connected to the core pack and the first transmission terminal, and is configured to output a voltage signal associated with the state of the core pack through the first transmission terminal. The non-volatile memory is electrically connected to the second transmission terminal, and is configured to receive and store information associate with the core pack through the second transmission terminal.

Abstract: Disclosed herein are second near-infrared (NIR-II) fluorescent composite and its production method. The method mainly includes the steps of, mixing a gold nanocluster having a plurality of a thiol-based compound on its outer surface and alpha-glycerylphosphorylcholine (alpha-GPC) in a solvent to form a mixture; replacing the solvent with an inert gas; and heating the mixture at a temperature about 100-200° C. in the presence of the inert gas until at least a portion of the gold nanocluster is encapsulated by a capping layer consisting of alpha-GPC, thereby producing the NIR-II fluorescent composite. The thus-produced NIR-II fluorescent composite is characterized by having an emission wavelength covering NIR-II region detectable by specialized camera. Also encompassed in the present disclosure is a method for conducting in vivo bioimaging of a target area in a subject.

Abstract: A system includes a processor and a memory. The processor locates a first memory chip that is faulty in a memory. After the first memory chip is isolated or replaced, the processor may reset the first memory chip when other memory chips in the memory are maintained to work normally. When a fault occurs in a memory chip in the memory, after the first memory chip that is faulty is isolated or replaced, the processor may independently reset the first memory chip without affecting the other memory chips in the memory. Resetting the first memory chip enables the first memory chip to restore to normal. A memory chip that can be normally used is used as a redundant memory chip or may continue to be used.

Abstract: Apparatus and methods are provided downlink and uplink CSI and power control for subband full duplex (SBFD) system. In one novel aspect, two CSI-RS configurations are configured for DL CSI, one for the DL-only slots and one for the SBFD slots. In one embodiment, the UE performs channel estimation individually using the CSI-RS configured for the DL-only slots and the SBFD slots. In another embodiment, the CSI-RS signals are periodic or aperiodic. The periodicity of CSI-RS for SBFD slots and DL-only slots are different. In one embodiment, the UE receives a first SRS configuration for UL-only slots and a second SRS configuration for the SBFD slots, transmits the SRS signals on UL-only slots and SBFD slots based on the first SRS configuration and the second SRS configuration. In another novel aspect, the UE receives two different sets of power control parameters for UL-only slots and the SBFD slots.

Abstract: In a method of manufacturing a semiconductor device, an n-type source/drain epitaxial layer and a p-type source/drain epitaxial layer respectively formed, a dielectric layer is formed over the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer, a first opening is formed in the dielectric layer to expose a part of the n-type source/drain epitaxial layer and a second opening is formed in the dielectric layer to expose a part of the p-type source/drain epitaxial layer, and the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer respectively recessed. A recessing amount of the n-type source/drain epitaxial layer is different from a recessing amount of the p-type source/drain epitaxial layer.

Abstract: The present disclosure provides self-adaptive laborsaving crimping pliers including a connecting handle, a movable handle, and a pliers head arranged on one end of the connecting handle and the movable handle. The connecting handle is bifurcated to form connecting arms rotatably arranged on the pliers head and elastic support arms. The connecting arms forms a linkage between the connecting handle and the pliers head. The movable handle is bifurcated to form movable connecting arms and elastic driving arms. The movable connecting arms are rotatably arranged on the pliers head and forms a linkage between the movable handle and the pliers head. The elastic driving arms are rotatably arranged on the elastic support arms to make the movable handle rotatably connect with the connecting handle. Limiting portions are arranged on the elastic support arms. A tension spring is arranged between the limiting portions and the movable handle.

Abstract: A method is described. The method includes obtaining a relationship between a thickness of a contamination layer formed on a mask and an amount of compensation energy to remove the contamination layer, obtaining a first thickness of a first contamination layer formed on the mask from a thickness measuring device, and applying first compensation energy calculated from the relationship to a light directed to the mask.

Abstract: An artificial tanzanite comprises aluminosilicate and vanadium, wherein the content of the aluminosilicate is in a range from 1 mass % to 30 mass % and the content of the vanadium is in a range from 1000 ppm to 40000 ppm. The artificial tanzanite is prepared by a method comprising: providing a synthetic raw material, wherein the synthetic raw material comprises the aluminosilicate, silicon-containing oxide, vanadium-containing oxide, and calcium-containing salt; and heating the synthetic raw material to a synthetic temperature, and keeping the synthetic raw material under a synthetic pressure to carry out synthetic reaction to form the artificial tanzanite after a period of synthetic time.

Abstract: A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.

Abstract: The present disclosure provides an adapter circuit including a bus capacitor, a PMOS power transistor, and a sampling control module; a positive terminal of the bus capacitor is connected to a DC bus voltage, and a negative terminal of the bus capacitor is connected to a drain of the PMOS power transistor; a gate of the PMOS power transistor is connected to a drive signal, and a source of the PMOS power transistor is grounded; the sampling control module is used to obtain the drive signal by detecting an AC mains input voltage and a power-down voltage when the bus discharges, so as to turn off the PMOS power transistor after the AC mains input voltage reaches a peak value, and turn on the PMOS power transistor after the power-down voltage reaches a set voltage; the drive signal includes a PMOS Turn-on signal and a PMOS Turn-off signal.

Abstract: An artificial intelligence accelerator includes an external command dispatcher, a first data access unit, a second data access unit, a global buffer, an internal command dispatcher, and a data/command switch. The external command dispatcher receives an address and access information. The external command dispatcher sends the access information to one of the first data access unit and the second data access unit, the first data access unit receives first data from a storage device according to the access information, and sends the first data to the global buffer. The second data access unit receives second data from the storage device according to the access information, and sends the second data. The data/command switch receives the address and the second data from the second data access unit, and sends the second data to one of the global buffer and the internal command dispatcher.

Abstract: A hardware-aware zero-cost neural network architecture search system is configured to perform the following. A neural network search space is divided into multiple search blocks. Each of the search blocks includes multiple candidate blocks. The candidate blocks are guided and scored through a latent pattern generator. The candidate blocks in each of the search blocks are scored through a zero-cost accuracy proxy. One of the candidate blocks included in each of the search blocks is sequentially selected as selected candidate blocks, the selected candidate blocks are combined into multiple neural networks to be evaluated, and network potential of the neural networks to be evaluated is calculated according to scores of the selected candidate blocks. One neural network to be evaluated with the highest network potential is selected to determine the corresponding selected candidate blocks.

Abstract: An example security gate can include: an outer frame; an outer gate disposed within the outer frame, the outer gate defining a plane and having a plurality of outer gate vertical members, and the outer gate defining an inner gate opening; an inner gate disposed within the outer gate, the inner gate defining a plurality of inner gate vertical members, wherein the inner gate is configured to move vertically within the plane to control access through the inner gate opening, and wherein the plurality of inner gate vertical members are sized to telescope within the plurality of outer gate vertical members as the inner gate is moved; and a locking mechanism to lock the inner gate at a vertical position relative to the outer gate to define an accessible size of the inner gate opening.

Abstract: A wavelength conversion device includes a substrate, a reflection layer, a wavelength conversion layer, and a first optical layer. The wavelength conversion device has a central axis. The reflection layer is disposed on an upper surface of the substrate. The central axis is perpendicular to the upper surface. The wavelength conversion layer is disposed on the reflection layer and around the central axis, has a complete or partial annular shape, and includes a first region and two second regions. The first region is located between the second regions. The first optical layer is disposed on a surface of the wavelength conversion layer and corresponds to the first region. In an axial direction, an orthographic projection of the first optical layer on the upper surface is not overlapped with an orthographic projection of the second regions on the upper surface. The first optical layer includes first diffusing particles.

Abstract: In various examples, a printbar is formed from multiple modular fluid ejection subassemblies joined together through a molding process that provides for a continuous planar substrate surface. A mold may secure the modular fluid ejection subassemblies during a molding process in which a runner conveys a molding material to seams between the joined modular fluid ejection subassemblies.

Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.

Abstract: An example digital microfluidic device can include a hydrophobic electrowetting surface including an array of electrodes. The individual electrodes can have a shape with three or more sides. The array of electrodes can include a parking electrode and an adjacent electrode that is adjacent to the parking electrode. A cover can be positioned over the electrowetting surface at a gap distance sufficient to accommodate a liquid droplet between the cover and the electrowetting surface. A plurality of droplet barriers can be positioned on three or more sides of the parking electrode. The droplet barriers can constrain movement of a liquid droplet from the parking electrode to the adjacent electrode.