Patents by Inventor Hua-Chou Tseng

Hua-Chou Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190245084
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: HSIEN-YUAN LIAO, CHIEN-CHIH HO, CHI-HSIEN LIN, HUA-CHOU TSENG, HO-HSIANG CHEN, RU-GUN LIU, TZU-JIN YEH, YING-TA LU
  • Patent number: 10276716
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsien-Yuan Liao, Chien-Chih Ho, Chi-Hsien Lin, Hua-Chou Tseng, Ho-Hsiang Chen, Ru-Gun Liu, Tzu-Jin Yeh, Ying-Ta Lu
  • Patent number: 10243075
    Abstract: A method for semiconductor devices on a substrate includes using gate structures which serve as active gate structures in a MOSFET region, as dummy gate structures in a JFET region of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments, thereby forming an accurately dimensioned transistor channel.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: March 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hua-Chou Tseng, Han-Chung Lin
  • Patent number: 10102972
    Abstract: A method of forming a capacitor structure includes forming a first set of electrodes having a first electrode and a second electrode, wherein each electrode of the first set of electrodes has an L-shaped portion. The method further includes forming a second set of electrodes having a third electrode and a fourth electrode, wherein each electrode of the second set of electrodes has an L-shaped portion. The method further includes forming insulation layers between the first set of electrodes and the second set of electrodes. The method further includes forming a first L-shaped line plug connecting the first electrode to the third electrode, wherein an entirety of an outer surface of the first L-shaped line plug is recessed with respect to an outer surface of the L-shaped portion of the first electrode. The method further includes forming a second line plug connecting the second electrode to the fourth electrode.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chun Hua, Chung-Long Chang, Chun-Hung Chen, Chih-Ping Chao, Jye-Yen Cheng, Hua-Chou Tseng
  • Patent number: 10068836
    Abstract: An integrated circuit includes a substrate, a first inter-layer dielectric (ILD) layer over the substrate, and a gate strip having a first width formed in the first ILD layer. A conductive strip having a second width is provided on the gate strip, with the second width being greater than the first width. The conductive strip is positioned so that the gate strip is covered and a portion of the conductive strip extends over a top surface of the first ILD adjacent the gate strip. A second ILD layer is provided over the conductive strip and the first ILD layer with a contact plug extending through the second ILD layer to provide electrical contact to the conductive strip.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: September 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih Ho, Chih-Ping Chao, Hua-Chou Tseng, Chun-Hung Chen, Chia-Yi Su, Alex Kalnitsky, Jye-Yen Cheng, Harry-Hak-Lay Chuang
  • Publication number: 20180053850
    Abstract: A method for semiconductor devices on a substrate includes using gate structures which serve as active gate structures in a MOSFET region, as dummy gate structures in a JFET region of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments, thereby forming an accurately dimensioned transistor channel.
    Type: Application
    Filed: November 3, 2017
    Publication date: February 22, 2018
    Inventors: Hua-Chou TSENG, Han-Chung LIN
  • Publication number: 20170345930
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Application
    Filed: November 2, 2016
    Publication date: November 30, 2017
    Inventors: HSIEN-YUAN LIAO, CHIEN-CHIH HO, CHI-HSIEN LIN, HUA-CHOU TSENG, HO-HSIANG CHEN, RU-GUN LIU, TZU-JIN YEH, YING-TA LU
  • Patent number: 9818866
    Abstract: A method for semiconductor devices on a substrate includes using gate structures which serve as active gate structures in a MOSFET region, as dummy gate structures in a JFET region of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments, thereby forming an accurately dimensioned transistor channel.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hua-Chou Tseng, Han-Chung Lin
  • Publication number: 20170213780
    Abstract: An integrated circuit includes a substrate, a first inter-layer dielectric (ILD) layer over the substrate, and a gate strip having a first width formed in the first ILD layer. A conductive strip having a second width is provided on the gate strip, with the second width being greater than the first width. The conductive strip is positioned so that the gate strip is covered and a portion of the conductive strip extends over a top surface of the first ILD adjacent the gate strip. A second ILD layer is provided over the conductive strip and the first ILD layer with a contact plug extending through the second ILD layer to provide electrical contact to the conductive strip.
    Type: Application
    Filed: April 7, 2017
    Publication date: July 27, 2017
    Inventors: Chien-Chih HO, Chih-Ping CHAO, Hua-Chou TSENG, Chun-Hung CHEN, Chia-Yi SU, Alex KALNITSKY, Jye-Yen CHENG, Harry-Hak-Lay CHUANG
  • Patent number: 9711593
    Abstract: A semiconductor device and methods for forming the same are provided. The semiconductor device includes a first doped region and a second, oppositely doped, region both formed in a substrate, a first gate formed overlying a portion of the first doped region and a portion of the second doped region, two or more second gates formed over the substrate overlying a different portion of the second doped region, one or more third doped regions in the second doped region disposed only between the two or more second gates such that the third doped region and the second doped region having opposite conductivity types, a source region in the first doped region, and a drain region in the second doped region disposed across the second gates from the first gate.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hua-Chou Tseng, Meng-Wei Hsieh
  • Patent number: 9620421
    Abstract: A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: April 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih Ho, Chih-Ping Chao, Hua-Chou Tseng, Chun-Hung Chen, Chia-Yi Su, Alex Kalnitsky, Jye-Yen Cheng, Harry-Hak-Lay Chuang
  • Patent number: 9583564
    Abstract: A structure comprises a p-type substrate, a deep n-type well and a deep p-type well. The deep n-type well is adjacent to the p-type substrate and has a first conductive path to a first terminal. The deep p-type well is in the deep n-type well, is separated from the p-type substrate by the deep n-type well, and has a second conductive path to a second terminal. A first n-type well is over the deep p-type well. A first p-type well is over the deep p-type well.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: February 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Jenn Yu, Meng-Wei Hsieh, Shih-Hsien Yang, Hua-Chou Tseng, Chih-Ping Chao
  • Patent number: 9431251
    Abstract: A method of forming a semiconductor device includes patterning a first mask over a substrate defining a first opening. The substrate includes a first dopant type. The method includes implanting ions having a second dopant type through the first opening to form a first deep well. The method includes patterning a second mask over the substrate defining a second opening. The method includes implanting ions having the second dopant type through the second opening to form a second deep well, wherein an energy for implanting ions to form the second deep well is lower than an energy for implanting ions to form the first deep well. The method includes implanting ions having the first dopant type into the substrate to form a first well, wherein the energy for implanting ions to form the second deep well is greater than an energy for implanting ions to form the first well.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hua-Chou Tseng, Chien-Chih Ho
  • Publication number: 20160035888
    Abstract: A method for semiconductor devices on a substrate includes using gate structures which serve as active gate structures in a MOSFET region, as dummy gate structures in a JFET region of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments, thereby forming an accurately dimensioned transistor channel.
    Type: Application
    Filed: October 12, 2015
    Publication date: February 4, 2016
    Inventors: Hua-Chou TSENG, Han-Chung LIN
  • Patent number: 9196751
    Abstract: A method for simultaneously forming JFET devices and MOSFET devices on a substrate includes using gate structures which serve as active gate structures in the MOSFET region, as dummy gate structures in the JFET portion of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments. The transistor channel is therefore accurately dimensioned.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hua-Chou Tseng, Han-Chung Lin
  • Publication number: 20150162198
    Abstract: A method of forming a semiconductor device includes patterning a first mask over a substrate defining a first opening. The substrate includes a first dopant type. The method includes implanting ions having a second dopant type through the first opening to form a first deep well. The method includes patterning a second mask over the substrate defining a second opening. The method includes implanting ions having the second dopant type through the second opening to form a second deep well, wherein an energy for implanting ions to form the second deep well is lower than an energy for implanting ions to form the first deep well. The method includes implanting ions having the first dopant type into the substrate to form a first well, wherein the energy for implanting ions to form the second deep well is greater than an energy for implanting ions to form the first well.
    Type: Application
    Filed: February 19, 2015
    Publication date: June 11, 2015
    Inventors: Hua-Chou TSENG, Chien-Chih HO
  • Publication number: 20150155096
    Abstract: A method of forming a capacitor structure includes forming a first set of electrodes having a first electrode and a second electrode, wherein each electrode of the first set of electrodes has an L-shaped portion. The method further includes forming a second set of electrodes having a third electrode and a fourth electrode, wherein each electrode of the second set of electrodes has an L-shaped portion. The method further includes forming insulation layers between the first set of electrodes and the second set of electrodes. The method further includes forming a first L-shaped line plug connecting the first electrode to the third electrode, wherein an entirety of an outer surface of the first L-shaped line plug is recessed with respect to an outer surface of the L-shaped portion of the first electrode. The method further includes forming a second line plug connecting the second electrode to the fourth electrode.
    Type: Application
    Filed: February 3, 2015
    Publication date: June 4, 2015
    Inventors: Wei-Chun HUA, Chung-Long CHANG, Chun-Hung CHEN, Chih-Ping CHAO, Jye-Yen CHENG, Hua-Chou TSENG
  • Patent number: 8987825
    Abstract: A semiconductor device includes a substrate having a first type doping. The semiconductor device further includes a first deep well in the substrate, the first deep well having a second type doping. The semiconductor device further includes a second deep well in the substrate, the second deep well having the second type doping and being separated and above the first deep well. The semiconductor device further includes a first well over the second deep well, the first well having the first type doping and a gate structure over the first well.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hua-Chou Tseng, Chien-Chih Ho
  • Patent number: 8971014
    Abstract: A capacitor structure includes first and second sets of electrodes and a plurality of line plugs. The first set of electrodes has a first electrode and a second electrode formed in a first metallization layer among a plurality of metallization layers, wherein the first electrode and the second electrode are separated by an insulation material. The second set of electrodes has a third electrode and a fourth electrode formed in a second metallization layer among the plurality of metallization layers, wherein the third electrode and the fourth electrode are separated by the insulation material. The line plugs connect the second set of electrodes to the first set of electrodes.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chun Hua, Chung-Long Chang, Chun-Hung Chen, Chih-Ping Chao, Jye-Yen Cheng, Hua-Chou Tseng
  • Publication number: 20140361367
    Abstract: A semiconductor device includes a substrate having a first type doping. The semiconductor device further includes a first deep well in the substrate, the first deep well having a second type doping. The semiconductor device further includes a second deep well in the substrate, the second deep well having the second type doping and being separated and above the first deep well. The semiconductor device further includes a first well over the second deep well, the first well having the first type doping and a gate structure over the first well.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Inventors: Hua-Chou TSENG, Chien-Chih HO