Abstract: Methods, systems, and devices for error information storage for boot-up procedures are described. A memory system may detect an error associated with performing the boot-up procedure of the memory system and may store error information associated with the detected error in a persistent register at the memory system. In some cases, the memory system may additionally store the error information in a cache at the memory system. After storing the error information, the memory system may reset and, after resetting, may transfer the error information from the persistent register to a non-volatile memory device at the memory system. In cases that the memory system stores error information in the cache prior to the reset, the memory system may additionally transfer the error information from the cache to the non-volatile memory device.

Abstract: Methods, systems, and devices for dynamic voltage supply for memory circuit are described. An apparatus may adjust a supply voltage based on a process corner and a temperature of the memory system. An apparatus may include a memory array and a controller. The controller may determine a first temperature of the apparatus is less than a first temperature threshold at a first time. The controller may transition a voltage supplied to the controller from a first voltage level to a second voltage level based on determining the first temperature is less than the first temperature threshold. The controller may determine a second temperature is greater than a second temperature threshold at a second time. The controller may transition the voltage supplied to the controller from the second voltage level to the first voltage level based on determining the second temperature is greater than the second temperature threshold.

Abstract: A method and apparatus for maintaining a communication connection is applicable into an electronic device, the electronic device supports running of a first system and a second system, and the method includes: sending, by the first system, a heartbeat packet to an external device based on the heartbeat packet sending request, wherein the heartbeat packet is configured to maintain a communication connection between the electronic device and the external device; and receiving, by the first system, a heartbeat feedback packet sent by the external device. An electronic device, and a non-transitory computer-readable storage medium are further provided.

Abstract: A microwave-heating crisp plate includes a body defining a food-supporting surface and an outer surface opposite the food-supporting surface, and a coating applied over at least a portion of the outer surface. The coating includes a base polymer material defining a matrix, carbon nanotubes, and ferrite particles. The carbon nanotubes and the ferrite particles are dispersed throughout the matrix in a predetermined relative ratio and in a predetermined dispersal ratio with respect to the matrix.

Abstract: Methods, systems, and devices for error information storage for boot-up procedures are described. A memory system may detect an error associated with performing the boot-up procedure of the memory system and may store error information associated with the detected error in a persistent register at the memory system. In some cases, the memory system may additionally store the error information in a cache at the memory system. After storing the error information, the memory system may reset and, after resetting, may transfer the error information from the persistent register to a non-volatile memory device at the memory system. In cases that the memory system stores error information in the cache prior to the reset, the memory system may additionally transfer the error information from the cache to the non-volatile memory device.

Abstract: A network slice self-optimization method, a base station, and a storage medium are disclosed. The method may include acquiring optimization policy information and indicator threshold sent by a server, where the optimization policy information includes first network slice resource configuration information and a parameter optimization model, and the first network slice resource configuration information and the parameter optimization model are both from the second base station; acquiring a service-level agreement (SLA) indicator according to the first network slice resource configuration information and the parameter optimization model; and adjusting the first network slice resource configuration information, in response to a dissatisfaction of the SLA indicator with the indicator threshold, such that the SLA indicator satisfies the indicator threshold.

Abstract: Methods, systems, and devices for error information storage for boot-up procedures are described. A memory system may detect an error associated with performing the boot-up procedure of the memory system and may store error information associated with the detected error in a persistent register at the memory system. In some cases, the memory system may additionally store the error information in a cache at the memory system. After storing the error information, the memory system may reset and, after resetting, may transfer the error information from the persistent register to a non-volatile memory device at the memory system. In cases that the memory system stores error information in the cache prior to the reset, the memory system may additionally transfer the error information from the cache to the non-volatile memory device.

Abstract: Methods, systems, and devices for dynamic voltage supply for memory circuit are described. An apparatus may adjust a supply voltage based on a process corner and a temperature of the memory system. An apparatus may include a memory array and a controller. The controller may determine a first temperature of the apparatus is less than a first temperature threshold at a first time. The controller may transition a voltage supplied to the controller from a first voltage level to a second voltage level based on determining the first temperature is less than the first temperature threshold. The controller may determine a second temperature is greater than a second temperature threshold at a second time. The controller may transition the voltage supplied to the controller from the second voltage level to the first voltage level based on determining the second temperature is greater than the second temperature threshold.

Abstract: A device includes a substrate, a pull-down transistor over the substrate, a pass-gate transistor over the substrate, and a pull-up transistor over the substrate. The pull-up transistor includes a first gate structure and first source/drain epitaxy structures on opposite sides of the first gate structure, in which each of the first source/drain epitaxy structures comprises a first epitaxy layer and a second epitaxy layer over the first epitaxy layer, wherein a germanium concentration of the first epitaxy layer is higher than a germanium concentration of the second epitaxy layer.

Abstract: Disclosed are a central chirality induced spiro chiral tetradentate cyclometalated platinum (II) and palladium (II) complex-based circularly polarized luminescence material and an application thereof. Spiro chiral metal complex molecules can be autonomously induced by a whole tetradentate ligand to coordinate with metal ions in a less sterically hindered manner by means of a central chiral fragment La in the tetradentate ligand, to form an optically pure spiro chiral metal complex-based circularly polarized luminescence material, without need for chiral resolution. Moreover, the material has high chemical stability and thermal stability, and has important applications in circularly polarized luminescence devices.

Abstract: A two-step door opening mechanism for an oven is provided. A mechanical button and an electronic button are provided, the oven defining an oven cavity openable and closable by an oven door. A controller is provided. A digital valve, comprising a shaft configured to slide laterally between a first, unlocked position in which the shaft allows inward movement of the mechanical button and a second, locked position in which the shaft blocks the inward movement of the mechanical button. The electronic button, once actuated, is operable to cause the controller to direct the digital valve to move the shaft from the second, locked position into the first, unlocked position to unlock the mechanical button, and the mechanical button, once actuated, is operable to open the door when the shaft is in the first, unlocked position.

Abstract: A federated learning participant selection method and apparatus, and a device and a storage medium are disclosed. The method may include acquiring a plurality of participants to be selected; determining a data quality factor, a service factor and a stability factor of each participant to be selected respectively; and determining a selected participant based on the data quality factor, service factor and stability factor of the plurality of participants to be selected.

Abstract: A two-step door opening mechanism for an oven is provided. The mechanism includes first and second buttons, arranged side-by-side on a front panel of the oven, the oven defining an oven cavity openable and closable by an oven door, the first and second buttons being separately actuatable one after the other for providing two distinct actions to be performed to open the oven door. The first button, once actuated, is operable to unlock the second button, and the second button, once actuated, is operable to open the door when the second button is unlocked.

Abstract: A gesture recognition method is provided, including: obtaining a sub-image of a hand region in a target image, and determining multiple pieces of feature point position information corresponding to multiple feature points in the sub-image of the hand region; determining a first position feature vector based on the multiple pieces of feature point position information, where the first position feature vector represents a relative position relationship of any one of the multiple feature points relative to remaining feature points in the multiple feature points; determining a second position feature vector based on the multiple pieces of feature point position information, where the second position feature vector represents an absolute position relationship of the multiple feature points in the sub-image of the hand region; and outputting a recognition result of the sub-image of the hand region based on the first position feature vector and the second position feature vector.

Abstract: A heating appliance includes a housing having interior walls with interior surfaces defining a cooking chamber for heating food, a microwave heating source configured to generate microwave radiation for heating the food, and a hybrid easy-to-clean coating on at least a portion of the interior surfaces, the hybrid easy-to-clean coating including a microwave absorbing component and a super hydrophobic component.

Abstract: Provided is an electronic apparatus (100). The electronic apparatus (100) includes a housing assembly (10), a flexible screen module (20), and an electroacoustic device (40). The housing assembly (10) includes a first housing (12) and a second housing (14) movably disposed on the first housing (12). The flexible screen module (20) is disposed on the housing assembly. The electroacoustic device (40) is disposed in the housing assembly (10) and has a sound cavity (41a) defined therein. During a movement of the second housing (14) relative to the first housing (12), at least part of the flexible screen module (20) moves into or out of the housing assembly (10) and a volume of the sound cavity (41a) is variable.

Abstract: An image processing method and apparatus are provided. The image processing method includes obtaining a reference makeup image by using a preset method, where the preset method includes at least one of recognizing a target image or scanning a target QR code; obtaining a user image; and obtaining and displaying a target makeup image based on the reference makeup image and the user image, where the target makeup image is an image obtained by transferring a makeup in a first target face image in the reference makeup image to a second target face image in the user image.

Abstract: A device includes a substrate, a pull-down transistor over the substrate, a pass-gate transistor over the substrate, and a pull-up transistor over the substrate. The pull-up transistor includes a first gate structure and first source/drain epitaxy structures on opposite sides of the first gate structure, in which each of the first source/drain epitaxy structures comprises a first epitaxy layer and a second epitaxy layer over the first epitaxy layer, wherein a germanium concentration of the first epitaxy layer is higher than a germanium concentration of the second epitaxy layer.

Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

Abstract: A method includes forming a first semiconductor fin over a p-well region of a substrate; forming a second semiconductor fin over an n-well region of a substrate; forming a gate structure crossing the first semiconductor fin and the second semiconductor fin; performing an implantation process to form a source/drain doped region in the first semiconductor fin; etching the second semiconductor fin to form a recess therein; performing a first epitaxy process to grow a first epitaxy layer in the recess; performing a second epitaxy process to grow a second epitaxy layer over the first epitaxy process; etching the second epitaxy layer to round a corner of the second epitaxy layer; forming an interlayer dielectric (ILD) layer covering the first semiconductor fin and the second epitaxy layer, wherein no etching is performed to the first semiconductor fin after forming the gate structure and prior to forming the ILD layer.