Abstract: A synthesis and an application of a phosphatase degrader are provided. The phosphatase degrader is a compound represented by formula I, or a salt thereof, or a deuterated compound thereof, or a stereoisomer thereof, or a solvate thereof, or a hydrate thereof, or a prodrug thereof. The compound can be used as a phosphatase degrader, especially as an SHP2 protein degrader, can treat malignant diseases such as tumors, and has good application prospects.

Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

Abstract: The present disclosure involves methods, apparatuses, and computer-readable storage media for media scan in a memory system. In one example, a method for a memory system includes receiving commands from a host coupled to the memory system, wherein the memory system includes a memory device, the memory device includes a memory cell array, and the memory cell array includes a number of memory cells. The method further includes performing operations on the memory device based on the commands. The method further includes scanning at least a group of memory cells of the memory cell array by performing a number of scans within a scan period among the operations.

Abstract: An example memory controller and readable storage medium are disclosed. An example memory system includes: a non-volatile memory device and a memory controller coupled to the non-volatile memory device; the memory controller is configured to: determine whether data for the logical block address mapping of a received read command belongs to tables of a first class or tables of a second class, and confirm the heat of the data corresponding to the logical block address of the received read command; determine a level of the amount of drift of a threshold voltage of a memory cell corresponding to the logical block address, according to the heat of the data corresponding to the logical block address of the received read command; determine different read voltages that are correspondingly sent to the memory cell corresponding to the logical block address, according to different levels of the amount of drift.

Abstract: In certain aspects, a memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device. The non-volatile memory device includes a plurality of memory groups. Each of the memory groups includes a plurality of memory units. The memory controller is configured to perform at least one of a first wear-leveling process by swapping a first memory group of the memory groups and a second memory group of the memory groups based on a first group write count for the first memory group and a second group write count for the second memory group, or a second wear-leveling process by swapping a first memory unit of the memory units and a second memory unit of the memory units based on a first unit write count for the first memory unit and a second unit write count for the second memory unit.

Abstract: In certain aspects, a method for operating a non-volatile memory device is provided. The non-volatile memory device includes memory units. A write count of a first memory unit of the memory units is determined. In response to the write count of the first memory unit reaching one of preset values, a flipped bit count (FBC) of a second memory unit of the memory units that is physically adjacent to the first memory unit is obtained. In response to the FBC of the second memory unit exceeding a threshold, the second memory unit is refreshed.

Abstract: In an example, a memory controller is configured to: check whether a logical block address corresponding to a host read command is maintained in a write buffer; determine a level of an amount of drift corresponding to the logical block address if the logical block address is not maintained in the write buffer, where different levels of the amount of drift correspond to different read voltages; and send a read command to a non-volatile memory device according to the level of the amount of drift corresponding to the logical block address. At least two of the processes of checking whether the logical block address is maintained, determining the level of the amount of drift, or sending the read command are performed in parallel.

Abstract: The present disclosure provides a coating for battery separator, a preparation method thereof, a battery separator and a battery, where a coating slurry of the coating for the battery separator includes a dispersion medium, a nanomaterial, and a polymer containing polar functional groups; the coating has a surface pore size of 10 nm-30 nm, and a surface roughness of 200 nm-500 nm, and the coating has a hydroxyl content of 100 mg KOH/g-4000 mg KOH/g. The coating for battery separator, the preparation method thereof, the battery separator and the battery can solve a problem of deformation of battery separators due to the induction of electrolyte solutions.

Abstract: A fan structure includes an upper frame defining a receiving space and at least one recess communicable with the receiving space; a stationary blade frame connected to a lower side of the upper frame, and internally forming a flared air passage having a stator seat provided therein; and an annular impeller externally provided with at least one inclined section corresponding to the recess. The annular impeller is mounted on the stator seat and located in the receiving space of the upper frame, and includes a hub, a plurality of blades, and an annular member. An impeller air passage is defined between the hub and the annular member and is communicable with the flared air passage to together form an inner airflow path. An outer side passage leading to the inclined section is defined between the annular member and the at least one recess to form an outer airflow path.

Abstract: A memory component has a block of memory cells that has been designated as a bad block. A processing device included in the memory component identifies a functional page of memory cells in the bad block, and programs system data to the identified functional page of memory cells in the bad block.

Abstract: Methods, systems, and devices for two-stage buffer operations supporting write commands are described. If data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment. To avoid die misalignment, a memory system may support two buffers for write data: a flush buffer and a temporary buffer. The memory system may determine whether to add received data to the flush buffer, the temporary buffer, or a combination thereof based on a data transfer size and a threshold size. If the data in the temporary buffer satisfies a copy condition, the data in the temporary buffer is copied into the flush buffer. If the data in the flush buffer satisfies a flush condition, the data in the flush buffer is written to the memory device starting at a multi-plane page offset of zero.

Abstract: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed.

Abstract: A method of interfacing a discrete digital workshop information system is provided, where the information system includes mutual integration among product lifecycle management (PLM), enterprise resource planning (ERP), a manufacturing execution system (MES), an energy management system (EMS), and a warehouse management system (WMS) of a finished product. A method of interfacing based on a data dictionary fusing different function datasets is proposed to solve the problems of a current discrete industry information system, such as single in function, a small amount of integrated information, a large number of “information islands” existing, incapable of achieving full-process informatization management and control, difficulty in product quality tracing and the like. By the method, it is possible to realize flexible production in a discrete manufacturing industry, precise management and control of a production process, significant improvement in product quality and significant reduction in operating costs.

Abstract: The disclosure provides a device and method for rapidly changing temperatures of a sample. An example of the device include: a first plate; a second plate; and a heating/cooling layer disposed on either the first or second plate. The first plate and the second plate face each other and are configured to receive a fluid sample sandwiched therebetween. The method includes depositing the fluid sample on one or both of the two plates, pressing the plates to form a thin layer of the sample, and changing and/or maintaining the temperature of the sample. The device or method can be used in, for example, PCR.

Abstract: A semiconductor package includes a substrate having a top planar surface and a semiconductor die mounted on the top planar surface of the substrate. Bond wires electrically connect the semiconductor die to the substrate. Flow control dams are integrally formed with the top planar surface of the substrate and each flow control dam protrudes from the top planar surface of the substrate at a location proximate to the bond wires. The flow control dams reduce the occurrence of wire sweep in the bond wires electrically connected to the substrate and semiconductor die.

Abstract: The disclosure provides a device and a method to press a QMAX-Card to form a liquid layer. A device comprises a first arm including a pressing block and a second arm including a compartment for accommodating the QMAX-Card. Each of the first arm and the second arm comprises a first end and a second end opposing the first end, and the first arm and the second arm are joined by a hinge at the first end. The first arm is capable of rotating around the hinge toward the second arm 500 from an open position to a close position. The pressing block and the compartment face each other and are disposed at the second end. The pressing block press the QMAX-Card so that the QMAX-Card changes a closed configuration to compress a liquid sample in the QMAX-Card into a substantially uniform thin layer.

Abstract: A memory controller coupled to a memory device including an array of memory cells, each memory cell being set to one of 2N states corresponding to a piece of N-bits data, where N is an integer greater than 1, and the array of memory cells being partitioned into one or more units. The memory controller is coupled to the memory device and configured to, upon executing instructions, obtain, from the memory device, a number P of memory cells in a unit of the units that are in one or more programmed states of the 2N states; calculate, based on the number P, a compensated read voltage with an offset from a default read voltage; and provide, to the memory device, the compensated read voltage for a read operation performed on a selected memory cell of the memory cells in a unit of the units.

Abstract: A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The first stack of memory dies includes a first substack of staggered memory dies offset with respect to each other in a first direction and a second substack of staggered memory dies offset with respect to each other in the first direction and positioned above the first substack. The second stack of memory dies includes a third substack of staggered memory dies offset with respect to each other in a second direction and a fourth substack of staggered memory dies offset with respect to each other in the second direction and positioned above the third substack. The top memory die of the first substack and a memory die positioned below the top memory die of the third substack are at least partially coplanar.

Abstract: An asymmetric organic photovoltaic acceptor material in an A-D-D?-A type is provided. A backbone containing noncovalent conformational lock is co-constructed with alkoxyindenothiophene and cyclopentadithiophene two-electron donor (D-D?) unit, and the ends are modified with fluorine- and chlorine-atom-substituted 3-(dicyanomethylidene)inden-1-one. The acceptor containing only a simple condensed ring has multiple advantages such as a coplanar backbone, low energy disorder, and J-aggregation tendency, and this type of asymmetric small-molecule acceptor has a controllably adjustable optical bandgap in the range of 1.30-1.45 eV, which is capable of combining with most donor materials to construct highly efficient binary bulk heterojunction organic solar cell. When the donor material is polymer PM6, the photoelectric conversion efficiency of the binary organic solar cells (OSCs) device is as high as 13.67%, with an open-circuit voltage (Voc) of 0.85 eV and energy loss (Eloss) is only 0.50 V.

Abstract: An asymmetric organic photovoltaic acceptor material in an A-D-D?-A type is provided. A backbone containing noncovalent conformational lock is co-constructed with alkoxyindenothiophene and cyclopentadithiophene two-electron donor (D-D?) unit, and the ends are modified with fluorine- and chlorine-atom-substituted 3-(dicyanomethylidene)inden-1-one. The acceptor containing only a simple condensed ring has multiple advantages such as a coplanar backbone, low energy disorder, and J-aggregation tendency, and this type of asymmetric small-molecule acceptor has a controllably adjustable optical bandgap in the range of 1.30-1.45 eV, which is capable of combining with most donor materials to construct highly efficient binary bulk heterojunction organic solar cell. When the donor material is polymer PM6, the photoelectric conversion efficiency of the binary organic solar cells (OSCs) device is as high as 13.67%, with an open-circuit voltage (Voc) of 0.85 eV and energy loss (Eloss) is only 0.50 V.