Abstract: Examples provide for error correction. The error correction includes: obtaining first soft data according to first hard read data and cached second hard read data after hard decision decoding for the first hard read data fails, wherein the first hard read data is read according to a first hard read voltage, and the second hard read data is read according to a second hard read voltage before reading the first hard read data; and performing first soft decision decoding according to the first soft data and the first hard read data, or according to the first soft data and the second hard read data, wherein the first hard read voltage is one of a plurality of re-read voltages corresponding to a read command; and the second hard read voltage is an initial read voltage or a re-read voltage of the plurality of re-read voltages except the first hard read voltage.

Abstract: In examples, a method of controlling a memory system comprises obtaining a first soft-bit data corresponding to a hard-bit data read from a memory and a first lookup table, where the first lookup table comprises a first log-likelihood ratio determined based on a first reference read voltage of the memory. The method comprises performing a first soft decoding operation according to the first log-likelihood ratio and the first soft-bit data. The method comprises performing at least one shift to the first log-likelihood ratio and performing a second soft decoding operation according to a log-likelihood ratio after each shift and the first soft-bit data when the first soft decoding operation is determined to have failed to decode.

Abstract: The application belongs to the technical field of signal acquisition, and discloses a stacked large-capacity signal acquisition and transmission system, which includes an adapter board, n acquisition boards, central control boards and a communication board sequentially laminated; where a circuit structure of each of the acquisition boards is the same; the adapter board is provided with circuit board interfaces and a plurality of first board-level connectors; an m-th acquisition board is provided with a signal acquisition and conditioning module, at least n-m+1 second board-level connectors and at least m third board-level connectors; the central control board is provided with a signal conversion module, at least one fourth board-level connector and at least one fifth board-level connector.

Abstract: The application belongs to the technical field of signal acquisition, and discloses a stacked large-capacity signal acquisition and transmission system, which includes an adapter board, n acquisition boards, central control boards and a communication board sequentially laminated; where a circuit structure of each of the acquisition boards is the same; the adapter board is provided with circuit board interfaces and a plurality of first board-level connectors; an m-th acquisition board is provided with a signal acquisition and conditioning module, at least n?m+1 second board-level connectors and at least m third board-level connectors; the central control board is provided with a signal conversion module, at least one fourth board-level connector and at least one fifth board-level connector.

Abstract: According to one aspect, the present disclosure provides a decoder. The decoder may include a posterior probability storage module that stores a posterior probability message respectively corresponding to each of a plurality of cyclic permutation matrices. The decoder may include a node message storage module that stores a message transmitted to a variable node by a check node respectively corresponding to each of the plurality of cyclic permutation matrices. The decoder may include a message updating module that sequentially receives the posterior probability message and the message transmitted to the variable node by the check node respectively corresponding to each of the plurality of cyclic permutation matrices in a first order, and sequentially outputs the updated message transmitted to the variable node by the check node and an updated posterior probability message respectively corresponding to each of the plurality of cyclic permutation matrices in a second order.

Abstract: The present disclosure provides a decoder including: a check node updating circuit and a variable node updating circuit. In a first time period, these circuits obtain the check node messages corresponding to different layers of the check matrix in the first updating units of different levels in the first updating units of a levels and obtain corresponding intermediate calculation values in the second updating units of different levels in the second updating units of a levels. After, the second updating units sequentially receive the check node messages corresponding to each layer of the check matrix and calculate the received check node messages with the intermediate calculation values of the second updating unit of the next level. From this, they obtain the variable node messages corresponding to different columns of the check matrix in the second updating units of different levels in the second updating units of a levels.

Abstract: A method for a memory system is disclosed. The memory system can include a memory controller and a memory device. The method can include receiving data that includes bits and is to be written into the memory device, counting a first bit number of the bits corresponding to a first state and a second bit number of the bits corresponding to the second state, and in response to the second bit number of the bits being larger than the first bit number of the bits, the flipping operation is performed.

Abstract: A method for a memory system is disclosed. The memory system can include a memory controller and a memory device. The method can include receiving data that includes bits and is to be written into the memory device, counting a first bit number of the bits corresponding to a first state and a second bit number of the bits corresponding to the second state, and in response to the second bit number of the bits being larger than the first bit number of the bits, the flipping operation is performed.

Abstract: Provided herein are methods and related apparatus for mask reconstruction in an etch process. The methods involve depositing a sacrificial layer on the mask layer. The sacrificial layer may be used to protect portions of the mask layer during reshaping by inhibiting etching of or deposition on the mask layer position on the mask layer. Following mask reshaping, the sacrificial layer may be removed using the same etch process that is used to etch the target material.

Abstract: A synthesis and an application of a phosphatase degrader are provided. The phosphatase degrader is a compound represented by formula I, or a salt thereof, or a deuterated compound thereof, or a stereoisomer thereof, or a solvate thereof, or a hydrate thereof, or a prodrug thereof. The compound can be used as a phosphatase degrader, especially as an SHP2 protein degrader, can treat malignant diseases such as tumors, and has good application prospects.

Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

Abstract: The present disclosure involves methods, apparatuses, and computer-readable storage media for media scan in a memory system. In one example, a method for a memory system includes receiving commands from a host coupled to the memory system, wherein the memory system includes a memory device, the memory device includes a memory cell array, and the memory cell array includes a number of memory cells. The method further includes performing operations on the memory device based on the commands. The method further includes scanning at least a group of memory cells of the memory cell array by performing a number of scans within a scan period among the operations.

Abstract: In certain aspects, a method for operating a non-volatile memory device is provided. The non-volatile memory device includes memory units. A write count of a first memory unit of the memory units is determined. In response to the write count of the first memory unit reaching one of preset values, a flipped bit count (FBC) of a second memory unit of the memory units that is physically adjacent to the first memory unit is obtained. In response to the FBC of the second memory unit exceeding a threshold, the second memory unit is refreshed.

Abstract: An example memory controller and readable storage medium are disclosed. An example memory system includes: a non-volatile memory device and a memory controller coupled to the non-volatile memory device; the memory controller is configured to: determine whether data for the logical block address mapping of a received read command belongs to tables of a first class or tables of a second class, and confirm the heat of the data corresponding to the logical block address of the received read command; determine a level of the amount of drift of a threshold voltage of a memory cell corresponding to the logical block address, according to the heat of the data corresponding to the logical block address of the received read command; determine different read voltages that are correspondingly sent to the memory cell corresponding to the logical block address, according to different levels of the amount of drift.

Abstract: In certain aspects, a memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device. The non-volatile memory device includes a plurality of memory groups. Each of the memory groups includes a plurality of memory units. The memory controller is configured to perform at least one of a first wear-leveling process by swapping a first memory group of the memory groups and a second memory group of the memory groups based on a first group write count for the first memory group and a second group write count for the second memory group, or a second wear-leveling process by swapping a first memory unit of the memory units and a second memory unit of the memory units based on a first unit write count for the first memory unit and a second unit write count for the second memory unit.

Abstract: In an example, a memory controller is configured to: check whether a logical block address corresponding to a host read command is maintained in a write buffer; determine a level of an amount of drift corresponding to the logical block address if the logical block address is not maintained in the write buffer, where different levels of the amount of drift correspond to different read voltages; and send a read command to a non-volatile memory device according to the level of the amount of drift corresponding to the logical block address. At least two of the processes of checking whether the logical block address is maintained, determining the level of the amount of drift, or sending the read command are performed in parallel.

Abstract: The present disclosure provides a coating for battery separator, a preparation method thereof, a battery separator and a battery, where a coating slurry of the coating for the battery separator includes a dispersion medium, a nanomaterial, and a polymer containing polar functional groups; the coating has a surface pore size of 10 nm-30 nm, and a surface roughness of 200 nm-500 nm, and the coating has a hydroxyl content of 100 mg KOH/g-4000 mg KOH/g. The coating for battery separator, the preparation method thereof, the battery separator and the battery can solve a problem of deformation of battery separators due to the induction of electrolyte solutions.

Abstract: A fan structure includes an upper frame defining a receiving space and at least one recess communicable with the receiving space; a stationary blade frame connected to a lower side of the upper frame, and internally forming a flared air passage having a stator seat provided therein; and an annular impeller externally provided with at least one inclined section corresponding to the recess. The annular impeller is mounted on the stator seat and located in the receiving space of the upper frame, and includes a hub, a plurality of blades, and an annular member. An impeller air passage is defined between the hub and the annular member and is communicable with the flared air passage to together form an inner airflow path. An outer side passage leading to the inclined section is defined between the annular member and the at least one recess to form an outer airflow path.

Abstract: A memory component has a block of memory cells that has been designated as a bad block. A processing device included in the memory component identifies a functional page of memory cells in the bad block, and programs system data to the identified functional page of memory cells in the bad block.

Abstract: Methods, systems, and devices for two-stage buffer operations supporting write commands are described. If data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment. To avoid die misalignment, a memory system may support two buffers for write data: a flush buffer and a temporary buffer. The memory system may determine whether to add received data to the flush buffer, the temporary buffer, or a combination thereof based on a data transfer size and a threshold size. If the data in the temporary buffer satisfies a copy condition, the data in the temporary buffer is copied into the flush buffer. If the data in the flush buffer satisfies a flush condition, the data in the flush buffer is written to the memory device starting at a multi-plane page offset of zero.