Abstract: The present invention provides, among other things, the devices and methods that can rapidly change or cycle (i.e. heat and cool) a sample temperature with high speed, less heating energy, high energy efficiency, a compact and simplified apparatus (e.g. handheld), easy and fast operation, and/or low cost.

Abstract: A memory system includes a memory device including memory cells, and a memory controller coupled to the memory device. A memory cell is configured to be programmed to one of a first state and a second state. The first state corresponds to a first bit, and the second state corresponds to a second bit. The memory controller is configured to receive first data including bits, the bits of the first data including the first bit and the second bit, in response to a second number of the second bit in the first data being larger than a first number of the first bit in the first data, perform a first flipping operation to the first data to obtain a second data including the bits, and store the second data to the memory device.

Abstract: Examples of the present application relate to a method of operating a memory system, a controller, a memory system and an electronic device, and relate to but are not limited to the field of memory technology. In an example, a method includes: in response to receiving a first command comprising a first logical address of first data on which an operation is to be performed, determining at least one zone corresponding to the first logical address, the at least one zone corresponding to a first storage space of a memory of the memory system, obtaining at least one first physical page address corresponding to the at least one zone according to a first mapping relationship and the at least one zone determined, and performing the operation on the first data in the first storage space according to the at least one first physical page address.

Abstract: The present disclosure provides a memory system with a non-volatile memory that includes a plurality of storage areas. Each storage may include a plurality of first storage groups in a first area and a plurality of second storage groups in a second area. The first area may support physical addressing. The second area may not support physical addressing. A memory controller of the memory system may perform a wear leveling process by swapping a first storage group having a first group write count with a second storage group having a second group write count. The first group write count may be a maximum group write count among a plurality of group write counts corresponding to the plurality of first storage groups. The second group write count may be a minimum group write count among a plurality of group write counts corresponding to the plurality of second storage groups.

Abstract: Aspects of the disclosure are directed to a memory system that can include a controller and a memory coupled thereto, each memory cell of the memory is configured to store m-bit information, and the controller includes at least one of an exclusive OR circuit, an inverter and an access circuit. The controller is configured to receive n groups of logic page data, and generate, at different values of m and n, at least one group of logic page data selectively by at least one of the exclusive OR circuit, the inverter and the access circuit. The controller is further configured to transmit the m groups of logic page data to the memory to generate 2n different data states in the memory.

Abstract: Examples of present disclosure disclose a memory device and an operation method thereof, and a readable storage medium. The memory device includes: a first memory region and a second memory region, each including a plurality of memory cells; and a peripheral circuit coupled with the first memory region and the second memory region and configured to: when writing data to the first memory region, perform a first program operation on memory cells to be programmed in the first memory region by using first program voltages that increase gradually; and when writing data in the first memory region to the second memory region, perform a second program operation on memory cells to be programmed in the second memory region by using second program voltages that increase gradually.

Abstract: Examples provide for error correction. The error correction includes: obtaining first soft data according to first hard read data and cached second hard read data after hard decision decoding for the first hard read data fails, wherein the first hard read data is read according to a first hard read voltage, and the second hard read data is read according to a second hard read voltage before reading the first hard read data; and performing first soft decision decoding according to the first soft data and the first hard read data, or according to the first soft data and the second hard read data, wherein the first hard read voltage is one of a plurality of re-read voltages corresponding to a read command; and the second hard read voltage is an initial read voltage or a re-read voltage of the plurality of re-read voltages except the first hard read voltage.

Abstract: The present disclosure provides a memory system with a non-volatile memory that includes a plurality of storage areas. Each storage may include a plurality of first storage groups in a first area and a plurality of second storage groups in a second area. The first area may support physical addressing. The second area may not support physical addressing. A memory controller of the memory system may perform a wear leveling process by swapping a first storage group having a first group write count with a second storage group having a second group write count. The first group write count may be a maximum group write count among a plurality of group write counts corresponding to the plurality of first storage groups. The second group write count may be a minimum group write count among a plurality of group write counts corresponding to the plurality of second storage groups.

Abstract: The disclosure relates to a device and method of using the device for performing biological and chemical assays that require an easy sample manipulation and/or a rapid change or a rapid thermal cycling of a sample temperature (e.g., Polymerase Chain Reaction (PCR) for amplifying nucleic acids). The device includes a first plate, a second plate, a plurality of spacers, and at least one clamp. The method includes obtaining the device, depositing a sample onto a sample contact area of at least one of the first and second plates of the device in an open configuration, closing the two plates into a closed configuration and placing the clamp in the active mode, and rapidly changing the temperature of the sample portion encircled by rings.

Abstract: A semiconductor wafer includes semiconductor dies and laser grooves formed in the scribe lines along the long edges of the semiconductor dies. A laser groove extends between the long edges of two adjacent semiconductor dies to encompass the corners of the two adjacent semiconductor dies. When diced, the resulting semiconductor dies have portions of the corners removed.

Abstract: According to one aspect of the present disclosure, a decoder is provided. The decoder may include a cache module. The cache module may be configured to cache soft data related to a codeword to be decoded. The decoder may include a flip-indication module. The flip-indication module may be configured to obtain the soft data from the cache module. The flip-indication module may be configured to, when performing hard-decision decoding on the codeword to be decoded, determine, at least in a first flip iteration and with assistance of the soft data, a number of parity checks not satisfied by bits in the codeword to be decoded.

Abstract: A method of interfacing a discrete digital workshop information system is provided, where the information system includes mutual integration among product lifecycle management (PLM), enterprise resource planning (ERP), a manufacturing execution system (MES), an energy management system (EMS), and a warehouse management system (WMS) of a finished product. A method of interfacing based on a data dictionary fusing different function datasets is proposed to solve the problems of a current discrete industry information system, such as single in function, a small amount of integrated information, a large number of “information islands” existing, incapable of achieving full-process informatization management and control, difficulty in product quality tracing and the like. By the method, it is possible to realize flexible production in a discrete manufacturing industry, precise management and control of a production process, significant improvement in product quality and significant reduction in operating costs.

Abstract: A method for patterning a stack having a mask with a plurality of mask features is provided. A targeted deposition is provided, wherein the targeted deposition comprises a plurality of cycles, wherein each cycle comprises flowing a precursor to deposit a layer of precursor and targeted curing the layer of precursor, comprising flowing a curing gas, flowing a modification gas, forming a plasma from the curing gas and modification gas, and exposing the layer of precursor to the plasma providing a targeted curing, wherein plasma from the curing gas cures first portions of the layer of precursor and plasma from the modification gas modifies second portions of the layer of precursor, wherein the modification of the second portion reduces curing of the layer of precursor of the second portions of the layer of precursor. The stack is etched through the targeted deposition.

Abstract: Methods, systems, and devices for dynamic voltage supply for memory circuit are described. An apparatus may adjust a supply voltage based on a process corner and a temperature of the memory system. An apparatus may include a memory array and a controller. The controller may determine a first temperature of the apparatus is less than a first temperature threshold at a first time. The controller may transition a voltage supplied to the controller from a first voltage level to a second voltage level based on determining the first temperature is less than the first temperature threshold. The controller may determine a second temperature is greater than a second temperature threshold at a second time. The controller may transition the voltage supplied to the controller from the second voltage level to the first voltage level based on determining the second temperature is greater than the second temperature threshold.

Abstract: The present application discloses a memory, a memory system, and a method for operating memory, which belongs to the memory techniques field. The method for operating memory comprises determining a storage state of a reference memory cell, determining a discharge duration of a sensing node corresponding to a target memory cell based on the storage state of the reference memory cell, and reading the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell to obtain read results. The target memory cell and the reference memory cell are located in the same string and are adjacent, and the programming order of the reference memory cell is after that of the target memory cell. The present application may reduce the influence on reading memory cells by interlayer interference and improve the accuracy of reading memory cells.

Abstract: The present disclosure provides a decoder including: a check node updating circuit and a variable node updating circuit. In a first time period, these circuits obtain the check node messages corresponding to different layers of the check matrix in the first updating units of different levels in the first updating units of ? levels and obtain corresponding intermediate calculation values in the second updating units of different levels in the second updating units of ? levels. After, the second updating units sequentially receive the check node messages corresponding to each layer of the check matrix and calculate the received check node messages with the intermediate calculation values of the second updating unit of the next level. From this, they obtain the variable node messages corresponding to different columns of the check matrix in the second updating units of different levels in the second updating units of ? levels.

Abstract: In examples, a method of controlling a memory system comprises obtaining a first soft-bit data corresponding to a hard-bit data read from a memory and a first lookup table, where the first lookup table comprises a first log-likelihood ratio determined based on a first reference read voltage of the memory. The method comprises performing a first soft decoding operation according to the first log-likelihood ratio and the first soft-bit data. The method comprises performing at least one shift to the first log-likelihood ratio and performing a second soft decoding operation according to a log-likelihood ratio after each shift and the first soft-bit data when the first soft decoding operation is determined to have failed to decode.

Abstract: Examples provide for error correction. The error correction includes: obtaining first soft data according to first hard read data and cached second hard read data after hard decision decoding for the first hard read data fails, wherein the first hard read data is read according to a first hard read voltage, and the second hard read data is read according to a second hard read voltage before reading the first hard read data; and performing first soft decision decoding according to the first soft data and the first hard read data, or according to the first soft data and the second hard read data, wherein the first hard read voltage is one of a plurality of re-read voltages corresponding to a read command; and the second hard read voltage is an initial read voltage or a re-read voltage of the plurality of re-read voltages except the first hard read voltage.

Abstract: A fan frame with noise muffling structure includes a frame having a top and a bottom and defining a centered air flow passage that extends from the top to the bottom. The air flow passage has an air inlet and an air outlet formed on the top and the bottom, respectively. The frame further has a noise muffling zone in at least one area of the frame located between the air flow passage and an outer periphery of the frame. In the noise muffling zone, there is provided at least one noise muffling unit, which is located between the top and the bottom without communicating with the air flow passage. The noise muffling unit internally defines a hollow cavity, which is closed between but not extended through the top and the bottom. The hollow cavity isolates air flow noise and absorbs frame vibration and noise produced by the frame vibration.

Abstract: The present disclosure provides a decoder including: a check node updating circuit and a variable node updating circuit. In a first time period, these circuits obtain the check node messages corresponding to different layers of the check matrix in the first updating units of different levels in the first updating units of a levels and obtain corresponding intermediate calculation values in the second updating units of different levels in the second updating units of a levels. After, the second updating units sequentially receive the check node messages corresponding to each layer of the check matrix and calculate the received check node messages with the intermediate calculation values of the second updating unit of the next level. From this, they obtain the variable node messages corresponding to different columns of the check matrix in the second updating units of different levels in the second updating units of a levels.