Abstract: Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.

Abstract: Methods, systems, and devices for dynamic power control are described. In some examples, a memory device may be configured to adjust a first duration for transitioning power modes. For example, the memory device may be configured to operate in a first power mode, a second power mode, and a third power mode. When operating in a second power mode, the memory device may be configured to increase or decrease the first duration for transitioning to a third power mode based on a second duration between received commands. If no commands are received during the first duration, the memory device may transition from the second power mode to the third power mode.

Abstract: Examples of computing devices for establishing a communication link with a remote device to contact a remote technical support service are described herein. In an example, a computing device may include a cellular communication interface and a processor. The processor may receive a first user input indicative of contacting a remote technical support service for the computing device. Based on the first user input, the processor may further establish a communication link between the computing device and a remote device over the cellular communication interface to contact the remote technical support service when the computing device is unbootable.

Abstract: A system includes a memory component and a processing device operatively coupled with the memory component. The processing device performs a test of the memory component by generating an error correction code (ECC) value for an initial operation of the test based on an address in the memory component on which the initial operation of the test is performed, generating ECC values for subsequent operations of the test, and reporting the ECC value generated for the last of the subsequent operations of the test in an event log. The ECC value for each respective subsequent operation of the test is generated based on an address in the memory component on which that respective subsequent operation of the test is performed, and the ECC value generated for the operation of the test that was performed immediately before that respective subsequent operation.

Abstract: A system includes a memory component and a processing device operatively coupled with the memory component. The processing device performs a test of the memory component by generating an error correction code (ECC) value for an initial operation of the test based on an address in the memory component on which the initial operation of the test is performed, generating ECC values for subsequent operations of the test, and reporting the ECC value generated for the last of the subsequent operations of the test in an event log. The ECC value for each respective subsequent operation of the test is generated based on an address in the memory component on which that respective subsequent operation of the test is performed, and the ECC value generated for the operation of the test that was performed immediately before that respective subsequent operation.

Abstract: Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.

Abstract: The present invention provides devices, systems, and methods for rapid and easy-to-use in sample thermal cycling or temperature changes for the facilitation of reactions such as but not limited to PCR.

Abstract: A multi-level memory architecture scheme to dynamically balance a number of parameters such as power, thermals, cost, latency and performance for memory levels that are progressively further away from the processor in the platform based on how applications are using memory levels that are further away from processor cores. In some examples, the decision making for the state of the far memory (FM) is decentralized. For example, a processor power management unit (p-unit), near memory controller (NMC), and/or far memory host controller (FMHC) makes decisions about the power and/or performance state of the FM at their respective levels. These decisions are coordinated to provide the most optimum power and/or performance state of the FM for a given time. The power and/or performance state of the memories adaptively change to changing workloads and other parameters even when the processor(s) is in a particular power state.

Abstract: The present disclosure provides a selection method of base asphalt for rubber asphalt based on grey relational analysis, which belongs to the technical field of selection methods of base asphalt. The selection method includes the following steps: determining factors affecting the performance of rubber asphalt and rubber asphalt performance evaluation indicators; ranking the factors affecting the performance of rubber asphalt according to respective affecting degrees thereof on each of the rubber asphalt performance evaluation indicators by using a grey relational method; and determining affecting factors of chemical components of base asphalt to the performance of rubber asphalt, and selecting base asphalt according to the affecting factors. The present disclosure uses the grey relational analysis method to systematically study the influences of chemical components of base asphalt on the performance of rubber asphalt.

Abstract: A method for identifying an AhR-phospho-ROR?t protein complex inhibitor, comprising: (a) providing a cell culture, in which cells in the culture express AhR protein and phospho-ROR?t protein; (b) incubating the cell culture in the presence of a test agent; (c) assaying the level of the AhR-phospho-ROR?t protein complex in the presence of the test agent; (d) comparing the level of the AhR-phospho-ROR?t protein complex in the presence of the test agent with a control; and (e) identifying the test agent as the inhibitor of the AhR-phospho-ROR?t protein complex when the comparing step indicates that there is a reduction in the level of the AhR-phospho-ROR?t protein complex in the presence of the test agent as compared with the control. A method for identifying a GLK?IQGAP1 protein complex inhibitor is also disclosed. Use of identified inhibitors in the manufacture of a medicament for treating a disease is also disclosed.

Abstract: A memory component has a block of memory cells that has been designated as a bad block. A processing device included in the memory component identifies a functional page of memory cells in the bad block, and programs system data to the identified functional page of memory cells in the bad block.

Abstract: Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.

Abstract: Methods, systems, devices, and computer-readable media are disclosed for performing read disturb management of a memory device. In one embodiment, a method is disclosed comprising retrieving a value of a read counter for a block associated with a read request issued to a memory array; refreshing valid word lines in the block if the value of the read counter exceeds a first threshold; identifying a set of valid word lines in the block if the value of the read counter exceeds a second threshold, the second threshold lower than the first threshold; identifying a subset of the set of valid word lines, the subset of the set of valid word lines including word lines having an error rate above a pre-configured error rate threshold; and refreshing the subset of the set of valid word lines.

Abstract: A memory device comprises a memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

Abstract: An electronic device having an enclosure formed from at least one glass cover and a peripheral structure formed adjacent the periphery of the glass cover is disclosed. The peripheral structure can be secured adjacent to the glass cover with an adhesive. The peripheral structure can be molded adjacent the glass cover so that a gapless interface is formed between the peripheral structure and the periphery of the glass cover. In one embodiment, the peripheral structure includes at least an inner peripheral structure and an outer peripheral structure.

Abstract: A memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

Abstract: A handshake communication mechanism between a host and an end-point device permits multiple Base Address Registers (BAR registers) to be configured to size or resize the mapped address spaces associated with each BAR register. In one embodiment, the handshake communication mechanism includes a single address space reconfiguration request which may be transmitted in a single transaction layer packet, to request the configuration of multiple BAR registers of an end-point device. Other features and advantages may be realized, depending upon the particular application.

Abstract: An electronic device having an enclosure formed from at least one glass cover and a peripheral structure formed adjacent the periphery of the glass cover is disclosed. The peripheral structure can be secured adjacent to the glass cover with an adhesive. The peripheral structure can be molded adjacent the glass cover so that a gapless interface is formed between the peripheral structure and the periphery of the glass cover. In one embodiment, the peripheral structure includes at least an inner peripheral structure and an outer peripheral structure.