Patents by Inventor Hua Tan

Hua Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230337384
    Abstract: An electronic device having an enclosure formed from at least one glass cover and a peripheral structure formed adjacent the periphery of the glass cover is disclosed. The peripheral structure can be secured adjacent to the glass cover with an adhesive. The peripheral structure can be molded adjacent the glass cover so that a gapless interface is formed between the peripheral structure and the periphery of the glass cover. In one embodiment, the peripheral structure includes at least an inner peripheral structure and an outer peripheral structure.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 19, 2023
    Inventors: David Pakula, Stephen Brian Lynch, Richard Hung Minh Dinh, Tang Yew Tan, Lee Hua Tan
  • Publication number: 20230323897
    Abstract: A fan frame turbulence structure includes a frame body having a wind incoming side and a wind outgoing side respectively on two sides of the frame body. The frame body defines an airflow passage which passes through the frame body from the wind incoming side to the wind outgoing side. The wind incoming side has an inlet in communication with the airflow passage. The inlet has a breaking section between the wind incoming side and the passage inner wall. The breaking section includes densely distributed breaking units. The breaking units define therebetween gaps in communication with the airflow passage. The breaking units serve to break and fracture airflow sucked in from the wind incoming side, whereby part of the airflow passes through the gaps between the breaking units and is broken and fractured into multiple gap turbulences to flow into the air passage so as to lower the wideband noise.
    Type: Application
    Filed: November 24, 2022
    Publication date: October 12, 2023
    Applicant: ASIA VITAL COMPONENTS (CHINA) CO., LTD.
    Inventors: Hua Lai, Ze-Hua Tan
  • Publication number: 20230307723
    Abstract: The invention relates to a battery module for an aerosol generating system. It comprises a battery extending substantially in a longitudinal direction and a printed circuit board assembly connected to the battery. The battery comprises along the longitudinal direction a first portion of a first thickness, and a second portion comprising opposite faces defining a second thickness, the second thickness being less than the first thickness. The printed circuit board assembly is electrically connected to the second portion of the battery on one of said opposite faces. This allows spatial optimization of the battery module. The invention also relates to a corresponding aerosol generating system, and to a corresponding set comprising a battery charger.
    Type: Application
    Filed: August 6, 2021
    Publication date: September 28, 2023
    Applicant: JT International SA
    Inventors: Pifa Shen, Zhinan Ming, Hua Tan, Jian Luo
  • Patent number: 11763899
    Abstract: Methods, systems, devices, and computer-readable media for performing read disturb management of a memory device. A method includes retrieving a value of a read counter for a block associated with a read request issued to a memory array; refreshing valid word lines in the block if the value of the read counter exceeds a first threshold; identifying a set of valid word lines in the block if the value of the read counter exceeds a second threshold, the second threshold lower than the first threshold; identifying a subset of the set of valid word lines, the subset of the set of valid word lines including word lines having an error rate above a pre-configured error rate threshold; and refreshing the subset of the set of valid word lines.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jun Jun Wang, Hua Tan
  • Publication number: 20230282594
    Abstract: A semiconductor wafer includes semiconductor dies and laser grooves formed in the scribe lines along the long edges of the semiconductor dies. A laser groove extends between the long edges of two adjacent semiconductor dies to encompass the corners of the two adjacent semiconductor dies. This prevents die cracking, for example during backgrind of the wafer. Moreover, the absence of laser grooves along the short edges of the semiconductor dies prevents die cracking, for example along short edges of dies overhanging empty space that are stressed during portions of the packaging process.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 7, 2023
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Chin-Tien Chiu, Jia Li, Dongpeng Xue, Huirong Zhang, Guocheng Zhong, Xiaohui Wang, Hua Tan
  • Publication number: 20230260975
    Abstract: A semiconductor device package includes a first substrate having an electrical circuit, semiconductor dies stacked one on top of the other, and bond wires electrically connected one to another. The bond wires electrically couple the semiconductor dies to one another and to the electrical circuit. There is a first bond wire having a first portion connected to a first semiconductor die, a second portion connected to a second semiconductor die, and an intermediate portion between the first portion and second portion. The semiconductor device package further includes a molding compound encapsulating the semiconductor dies, and the first and second portions of the first bond wire. The intermediate portion of the first bond wire is exposed along a top planar surface of the molding compound. The semiconductor device package may be used for coupling one or more other semiconductor device packages thereto via the exposed intermediate portion.
    Type: Application
    Filed: February 14, 2022
    Publication date: August 17, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Hua Tan, Hope Chiu, Weiting Jiang, Elley Zhang, Cong Zhang, Simon Dong, Jerry Tang, Rosy Zhao
  • Patent number: 11723165
    Abstract: An electronic device having an enclosure formed from at least one glass cover and a peripheral structure formed adjacent the periphery of the glass cover is disclosed. The peripheral structure can be secured adjacent to the glass cover with an adhesive. The peripheral structure can be molded adjacent the glass cover so that a gapless interface is formed between the peripheral structure and the periphery of the glass cover. In one embodiment, the peripheral structure includes at least an inner peripheral structure and an outer peripheral structure.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: August 8, 2023
    Assignee: APPLE INC.
    Inventors: David Pakula, Stephen Brian Lynch, Richard Hung Minh Dinh, Tang Yew Tan, Lee Hua Tan
  • Patent number: 11719685
    Abstract: The present disclosure provides a selection method of base asphalt for rubber asphalt based on grey relational analysis, which belongs to the technical field of selection methods of base asphalt. The selection method includes the following steps: determining factors affecting the performance of rubber asphalt and rubber asphalt performance evaluation indicators; ranking the factors affecting the performance of rubber asphalt according to respective affecting degrees thereof on each of the rubber asphalt performance evaluation indicators by using a grey relational method; and determining affecting factors of chemical components of base asphalt to the performance of rubber asphalt, and selecting base asphalt according to the affecting factors. The present disclosure uses the grey relational analysis method to systematically study the influences of chemical components of base asphalt on the performance of rubber asphalt.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: August 8, 2023
    Assignees: Guangxi Transportation Science and Technology Group Co., Ltd., Guangxi Jiaoke New Materials Technology Co., Ltd.
    Inventors: Honggang Zhang, Hua Tan, Jizong Tan, Haitao Yuan, Hongbo Zhang, Baolin Xiong, Jianping Xiong, Zehua Xie, Dongliang Kuang
  • Publication number: 20230246000
    Abstract: A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The first stack of memory dies includes a first substack of staggered memory dies offset with respect to each other in a first direction and a second substack of staggered memory dies offset with respect to each other in the first direction and positioned above the first substack. The second stack of memory dies includes a third substack of staggered memory dies offset with respect to each other in a second direction and a fourth substack of staggered memory dies offset with respect to each other in the second direction and positioned above the third substack. The top memory die of the first substack and a memory die positioned below the top memory die of the third substack are at least partially coplanar.
    Type: Application
    Filed: February 1, 2022
    Publication date: August 3, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Haiyue Shen, Fen Yu, Hope Chiu, Donghua Wu, Hua Tan, Xinyu Wang, Shenghua Huang
  • Patent number: 11704275
    Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Kuan Hua Tan, Eng Hun Ooi, Ang Li
  • Publication number: 20230219084
    Abstract: Among other things, the present invention is related to devices and methods of performing biological and chemical assays, particularly an easy sample manipulation and/or a rapid change or a rapid thermal cycling of a sample temperature is needed (e.g. Polymerase Chain Reaction (PCR) for amplifying nucleic acids).
    Type: Application
    Filed: March 14, 2023
    Publication date: July 13, 2023
    Applicant: Essenlix Corporation
    Inventors: Stephen Y. Chou, Wei Ding, Ji Qi, Hua Tan, Yufan Zhang
  • Publication number: 20230200454
    Abstract: An electronic vaporization device includes: a first conductor for accommodating an aerosol-generation product; a second conductor spaced apart from the first conductor; and a control unit for: obtaining an electrical parameter between the first conductor and the second conductor when the first conductor and the second conductor are electrically connected by the aerosol-generation product, obtaining a liquid content of the aerosol-generation product according to the electrical parameter, and controlling, according to the liquid content of the aerosol-generation product, a heating element to heat the aerosol-generation product.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 29, 2023
    Inventors: Jun LI, Zhaohuan ZENG, Hua TAN, Danchong HE, Pifa SHEN, Ruofei YAN, Tao CHEN
  • Patent number: 11687291
    Abstract: Methods, systems, and devices for memory operations are described. A first set of commands may be received for accessing a memory device. The first set of commands may include non-consecutive logical addresses that correspond to consecutively indexed physical addresses. A determination that the non-consecutive logical addresses correspond to consecutively indexed physical addresses may be determined based on a first mapping stored in a volatile memory. A second mapping may be transferred to the volatile memory based on the determination. The second mapping may include an indication of whether information stored at a set of physical address is valid. A second set of commands including non-consecutive logical addresses may be received for accessing the memory device. Data for the second set of commands that include the non-consecutive logical addresses may be retrieved from the memory device using the second mapping.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hua Tan, Fangwen Zhou, Wenjing Chen
  • Patent number: 11670375
    Abstract: A memory device provides a memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: June 6, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hua Tan, Jingxun Eric Wu, Yingying Zhu, Hui Yang, Bo Zhou
  • Patent number: 11648551
    Abstract: Among other things, the present invention is related to devices and methods of performing biological and chemical assays, particularly an easy sample manipulation and/or a rapid change or a rapid thermal cycling of a sample temperature is needed (e.g. Polymerase Chain Reaction (PCR) for amplifying nucleic acids).
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: May 16, 2023
    Assignee: Essenlix Corporation
    Inventors: Stephen Y. Chou, Wei Ding, Ji Qi, Hua Tan, Yufan Zhang
  • Publication number: 20230143181
    Abstract: Upon receipt of a synchronize cache command, valid host data size in the SRAM write buffer is checked. If the valid data size is greater than a predetermined value, valid host data in the SRAM write buffer is flushed directly into an open MLC block based on a one-pass transfer program. However, if the valid host data size is less than the predetermined value, the host data is not flushed to an open MLC block but is instead flushed into a temporary storage location to satisfy the command specifications for a command to synchronize a cache. The host data is maintained in the SRAM write buffer, which receives additional data until full. Once full, the host data in the SRAM write buffer is transferred to an open MLC block in one-pass. If the host data in the write buffer is lost, it may be recovered from the temporary storage location.
    Type: Application
    Filed: August 27, 2019
    Publication date: May 11, 2023
    Inventors: Hua Tan, Hui Yang, Mauro Luigi Sali
  • Publication number: 20230129628
    Abstract: A semiconductor device package includes a multi-layer substrate including a bottom layer and a top layer. One or more dies are mounted on and electrically coupled to the top layer of the substrate. An electromagnetic interference (EMI) shield encapsulates the substrate and the semiconductor dies. A first plurality of conductive stubs is positioned around edges of the top layer of the substrate. Each of the conductive stubs includes an edge portion having a first thickness and in contact with the EMI shield. A second plurality of conductive stubs is positioned around edges of the bottom layer of the substrate. Each of the second plurality of conductive stubs includes an edge portion having a second thickness less than the first thickness and in contact with the EMI shield.
    Type: Application
    Filed: October 25, 2021
    Publication date: April 27, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Simon Dong, Hope Chiu, Weiting Jiang, Elley Zhang, Kent Yang, Hua Tan, Jerry Tang, Rui Guo
  • Publication number: 20230120779
    Abstract: A heating control method includes: obtaining a current inhalation parameter according to an inhalation situation of a user; obtaining a corresponding target temperature threshold according to the current inhalation parameter, the target temperature threshold being progressively increased in a stepwise manner as the inhalation parameter increases; and detecting a current heating temperature value of a heating body, and adjusting the current heating temperature value of the heating body to the target temperature threshold.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 20, 2023
    Inventors: Zhihua WEN, Hua TAN, Houlin CHEN, Fenglei XING
  • Publication number: 20230107227
    Abstract: Methods, systems, and devices for two-stage buffer operations supporting write commands are described. If data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment. To avoid die misalignment, a memory system may support two buffers for write data: a flush buffer and a temporary buffer. The memory system may determine whether to add received data to the flush buffer, the temporary buffer, or a combination thereof based on a data transfer size and a threshold size. If the data in the temporary buffer satisfies a copy condition, the data in the temporary buffer is copied into the flush buffer. If the data in the flush buffer satisfies a flush condition, the data in the flush buffer is written to the memory device starting at a multi-plane page offset of zero.
    Type: Application
    Filed: March 1, 2021
    Publication date: April 6, 2023
    Inventors: Hua Tan, Lingye Zhou
  • Publication number: 20230102959
    Abstract: A semiconductor package includes a substrate having a top planar surface and a semiconductor die mounted on the top planar surface of the substrate. Bond wires electrically connect the semiconductor die to the substrate. Flow control dams are integrally formed with the top planar surface of the substrate and each flow control dam protrudes from the top planar surface of the substrate at a location proximate to the bond wires. The flow control dams reduce the occurrence of wire sweep in the bond wires electrically connected to the substrate and semiconductor die.
    Type: Application
    Filed: September 30, 2021
    Publication date: March 30, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Hope Chiu, Hua Tan, Kent Yang, Weiting Jiang, Jerry Tang, Simon Dong, Yuequan Shi, Rosy Zhao