Patents by Inventor Hua Tan

Hua Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120034738
    Abstract: A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds.
    Type: Application
    Filed: October 20, 2011
    Publication date: February 9, 2012
    Applicants: QIMONDA AG, UNITED TEST AND ASSEMBLY CENTER, LTD.
    Inventors: Denver Paul C. CASTILLO, Bryan Soon Hua TAN, Rodel MANALAC, Kian Teng ENG, Pang Hup ONG, Soo Pin CHOW, Wolfgang Johannes HETZEL, Werner Josef REISS, Florian AMMER
  • Publication number: 20120016608
    Abstract: This present disclosure provides a method and the system thereof for monitoring residential appliances, which includes: measuring electrical data in a residence and transmitting the electrical data to a local data-processing unit, the electrical data at least containing a voltage, a real power, and a reactive power; normalizing the electrical data according to the voltage; calculating a variation of the normalized electrical data when the electrical data change; and comparing the variation of the normalized electrical data to an electrical feature which is contained in appliance information of the local data-processing unit, so as to determine the appliance which causes the variation of the electrical data.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 19, 2012
    Applicant: Industrial Technology Research Institute
    Inventors: LEE-CHUN KO, CHIH-YUAN LIU, LUN-CHIA KUO, JUI-HUA TAN
  • Patent number: 8099655
    Abstract: A Galois Field multiplier circuit for multiplying two polynomials (multiplicands). The multiplier circuit can use any arbitrary primitive polynomial to preserve the Galois Field. The multiplier circuit includes at least one logic unit that receives as a first input one of the multiplicands and shift the multiplicand in question by 1 bit to the left. The logic unit receives as a second input a pre-determined primitive polynomial and multiplies the primitive polynomial by the highest bit of the multiplicand received at the other input of the logic unit. The bit-shifted multiplicand is XOR-ed with the primitive polynomial multiplied the highest bit of the multiplicand and the result of the XOR operation is provided to a second logic circuit that completes the multiplication of the two polynomials.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: January 17, 2012
    Assignee: PMC-Sierra US, Inc.
    Inventors: Kuan Hua Tan, Amr Wassal
  • Patent number: 8095722
    Abstract: A method and apparatus are provided for implementing connection management in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. The method and apparatus provides arbitration of connection requests to be setup or removed among multiple end devices and expander devices so as to increase system performance and reduce hardware cost in a standard compliant manner.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: January 10, 2012
    Assignee: PMC-Sierra US, Inc.
    Inventors: Heng Liao, Kuan Hua Tan, Calvin Leung
  • Patent number: 8087922
    Abstract: In imprint lithography, a mold having a pattern of projecting and recessed regions is pressed into a moldable surface on a substrate. The thus-imprinted moldable surface is permitted to at least partially harden to retain the imprint, and the substrate and mold are separated. In accordance with the invention, the substrate is separated from the mold by bending laterally distal regions (regions away from the center toward the edges) of the mold transversely away from the interface and transversely restraining the substrate. The mold can then be easily separated from the substrate by transverse displacement. The separation can be facilitated by providing a mold having a lateral dimension that on at least two sides extends beyond the corresponding lateral dimension of the substrate. Alternatively, the substrate can have a greater lateral extent than the mold, and the mold can be restrained. The distal regions of the substrate can be bent in the transverse direction.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: January 3, 2012
    Inventors: Wei Zhang, Hua Tan, Lin Hu, Stephen Y. Chou
  • Patent number: 8089902
    Abstract: A method and system are provided for broadcast message filtering in SAS expanders. Common SAS topology defined by ANSI T10 specification only supports spanning tree topology (without loops) interconnection among multiple end devices and expander devices. Broadcast message filtering provides a mechanism to selectively discard broadcast messages, or primitives, in the SAS expanders to break the infinite loop path that broadcast primitives can traverse. This enables new SAS physical topologies with loops that are otherwise difficult or impossible to realize using SAS expanders that handle primitive broadcasts according to the definition of the SAS standard. By allowing redundant paths in a SAS topology, the problem of infinite broadcast flooding in SAS topology is reduced. Selectively forwarding broadcast messages can be based on whether the broadcast was originated at the source phy, or received by the source phy, or based on whether the source phy is a filtered phy.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: January 3, 2012
    Assignee: PMC-Sierra US, Inc.
    Inventors: Heng Liao, Kuan Hua Tan, Larrie Simon Carr
  • Patent number: 8025829
    Abstract: In accordance with the invention, step-and-repeat imprint lithography is effected by applying balanced pressing forces from both sides of a substrate. The pressing forces are substantially equal in amplitude and opposite in direction. With the pressing forces thus balanced, the fixture that steps and holds the substrate does not bear the load of imprinting. The balance allows use of a high resolution aligning stage to carry the substrate and to maintain high accuracy of positioning without being shifted by change of load. With this method, sufficient imprint pressure can be used to obtain high quality patterning, a thin and uniform residual layer, and a high fidelity pattern.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: September 27, 2011
    Assignee: Nanonex Corporation
    Inventors: Wei Zhang, Hua Tan, Lin Hu, Stephen Y. Chou
  • Publication number: 20110180965
    Abstract: The invention disclosed apparatuses and methods to do nanoimprint lithography using a deformable mold. Generally, the apparatus has a chamber with a transparent section on its top wall, which is capable of vacuuming and pressurizing. The deformable mold fixed firmly onto a hollow mold holder around its full periphery is attached to top inner surface of the chamber and positioned underneath the transparent section. The central area of the mold is freely accessible from underneath through the opening of the mold holder. An enclosed volume referring to mold mini-chamber is formed between the mold/holder and top wall of the chamber. Inside chamber, a stage assembly is installed. A chuck to vacuumly hold a substrate is mounted on top of the stage assembly. At beginning of the imprinting, the substrate with a layer of resist is positioned underneath the mold at a predetermined gap between them. Then, the substrate is moved up to contact with the mold either under vacuum or under atmosphere.
    Type: Application
    Filed: January 21, 2011
    Publication date: July 28, 2011
    Applicant: NANONEX CORPORATION
    Inventors: Wei Zhang, Hua Tan, Lin Hu, Stephen Y. Chou
  • Publication number: 20110177026
    Abstract: The present invention provides methods for treating a flavivirus infection, including hepatitis C virus (HCV) infection, in an individual suffering from a flavivirus infection. In some embodiments, the methods involve administering to an individual in need thereof an effective amount of an agent that inhibits enzymatic activity of a membrane-bound ?-glucosidase inhibitor. In other embodiments, the methods involve administering to an individual in need thereof effective amounts of an ?-glucosidase inhibitor and at least one additional therapeutic agent.
    Type: Application
    Filed: February 10, 2011
    Publication date: July 21, 2011
    Applicant: INTERMUNE, INC.
    Inventors: Lawrence M. Blatt, Hua Tan, Scott D. Seiwert
  • Publication number: 20110155060
    Abstract: A surface coating apparatus for preparing a work piece having a working surface for imprint lithography, wherein the work piece comprises either a mold or a substrate. The apparatus includes a vacuum chamber and a generator to produce chemical reaction radicals for cleaning the working surface. The generator may be located inside said vacuum chamber and connected to an inner surface of said vacuum chamber or external to the vacuum chamber and connected thereto via suitable couplings. A fixture within the vacuum chamber is configured to hold the work piece with the working surface accessible by the chemical reaction radicals, and a means is provided for depositing a molecular layer of surfactant on the working surface inside the vacuum chamber.
    Type: Application
    Filed: February 15, 2011
    Publication date: June 30, 2011
    Inventors: Wei Zhang, Lin Hu, Hua Tan, Linshu Kong, Stephen Y. Chou
  • Patent number: 7958295
    Abstract: A method and apparatus are provided for finding the maxima and minima from a set of inputs data. Given a master set K[0 . . . N?1] of N keys, the current invention can pre-compute a comparison matrix, find the maximum key KMAX or minimum key KMIN from the master set K[0 . . . N?1] and indicate the key position index PMAX of the maximum key or PMIN of the minimum key. Given a subset S[0 . . . M?1] of M keys where the subset S[0 . . . M?1] belongs to the master set K[0 . . . N?1], the current invention can also find the maximum key SMAX or minimum key SMIN from the subset S[0 . . . M?1] and indicate the reference key position index PMAX of the maxima SMAX or PMIN of the minima SMIN in the master set K[0 . . . N?1]. The current invention can also find a specific rank of key (example 5th largest key or 6th smallest key) and return the reference key index position in the master set K[0 . . . N?1].
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: June 7, 2011
    Assignee: PMC-Sierra US, Inc.
    Inventors: Heng Liao, Kuan Hua Tan
  • Patent number: 7932267
    Abstract: The present invention provides methods for treating a flavivirus infection, including hepatitis C virus (HCV) infection, in an individual suffering from a flavivirus infection. In some embodiments, the methods involve administering to an individual in need thereof an effective amount of an agent that inhibits enzymatic activity of a membrane-bound ?-glucosidase inhibitor. In other embodiments, the methods involve administering to an individual in need thereof effective amounts of an ?-glucosidase inhibitor and at least one additional therapeutic agent.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: April 26, 2011
    Assignee: Intermune, Inc.
    Inventors: Lawrence M. Blatt, Hua Tan, Scott Seiwert
  • Patent number: 7893712
    Abstract: An integrated circuit, such as a field programmable gate array or other configurable logic device, has an interconnect circuit selectively configurable to operate in a high-speed mode or in a low-power mode. The interconnect circuit is operable from a higher voltage supply or a lower voltage supply to change operating modes without reconfiguring data paths.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: February 22, 2011
    Assignee: Xilinx, Inc.
    Inventors: Chin Hua Tan, Shankar Lakka, Ronald L. Cline, James B. Anderson, Wayne E. Wennekamp
  • Publication number: 20110039400
    Abstract: Disclosed is a method for fabrication of a semiconductor of gallium nitride arsenide antimonide (GaNAsSb) on a substrate wherein the fabrication is performed at a fabrication temperature followed by annealing at an annealing temperature for an annealing time; wherein at least one of: the fabrication temperature, annealing temperature and annealing time, is controlled for controlling defect formation in the semiconductor so as to achieve predetermined performance characteristics of the semiconductor.
    Type: Application
    Filed: June 26, 2008
    Publication date: February 17, 2011
    Applicant: Nanyang Technological University
    Inventors: Soon Fatt Yoon, Kian Hua Tan, Wan Khai Loke, Satrio Wicaksono, Tien Khee Ng
  • Patent number: 7861440
    Abstract: An ironing board includes a base, a body with a work surface and an easy height-adjustment operation to adjust the distance of the body relative to the base. A column extends between the body and the base and is equipped with a stationary frame secured to the base and a moveable frame secured to the body. In order to decrease the force needed to adjust the height of the body relative to the base, the height adjustment device includes device for exerting a repelling force between the body and the base.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: January 4, 2011
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Kok Wah Ma, Derrick Wai Thong Loke, Mong Hua Tan, Mohankumar Valiyambath Krishnan, Chandra Mohan Janakiraman, Swee Loon Michael Tang, Choon Hwee Tan
  • Patent number: 7856743
    Abstract: An ironing board (2) that can easily be stored and converted to a stable position for ironing comprises a base (1) having a variable length, and a body (5) with a work surface (6). A column (7) extends between the body and the base. An adjustment mechanism (9) arranges for the base to be shorter in case the work surface is positioned vertically and the base to be longer in case the work surface is positioned horizontally. A system comprises such an ironing board and an iron for cooperation with the ironing board.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: December 28, 2010
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Kok Wah Ma, Derrick Wai Thong Loke, Mong Hua Tan, Mohankumar Valiyambath Krishnan, Chandra Mohan Janakiraman, Swee Loon Michael Tang, Choon Hwee Tan
  • Publication number: 20100289184
    Abstract: In accordance with the invention, step-and-repeat imprint lithography is effected by applying balanced pressing forces from both sides of a substrate. The pressing forces are substantially equal in amplitude and opposite in direction. With the pressing forces thus balanced, the fixture that steps and holds the substrate does not bear the load of imprinting. The balance allows use of a high resolution aligning stage to carry the substrate and to maintain high accuracy of positioning without being shifted by change of load. With this method, sufficient imprint pressure can be used to obtain high quality patterning, a thin and uniform residual layer, and a high fidelity pattern.
    Type: Application
    Filed: July 27, 2010
    Publication date: November 18, 2010
    Inventors: Wei Zhang, Hua Tan, Lin Hu, Stephen Y. Chou
  • Publication number: 20100273862
    Abstract: The present invention provides novel JNK activating phosphatase polypeptides and nucleic acid molecules encoding the same. The invention also provides vectors, host cells, antibodies and methods for producing JNK activating phosphatase polypeptides. Also provided for are methods for the diagnosis and treatment of diseases associated with JNK activating phosphatase polypeptides.
    Type: Application
    Filed: January 22, 2007
    Publication date: October 28, 2010
    Applicants: Amgen Inc., Baylor College of Medicine
    Inventors: John W. Belmont, Frederick A. Fletcher, Alice J. Chen, Roland Jurecic, Tse-Hua Tan, Guisheng Zhou
  • Publication number: 20100244324
    Abstract: A mold for imprinting a patterned region by imprint lithography is provided with a peripheral groove around the patterned region. The groove is connected, as by channels through the mold, to a switchable source for gas removal to prevent bubbles and for the application of pressurized gas to separate the mold and substrate. In use, the mold is disposed adjacent the moldable surface and gas is withdrawn from the patterned region through the groove as the mold is pressed toward and into the moldable surface. At or near the end of the imprinting, the process is switched from removal of gas to the application of pressurized gas. The pressurized gas passes through the groove and separates or facilitates separation of the mold and the moldable surface.
    Type: Application
    Filed: June 7, 2010
    Publication date: September 30, 2010
    Applicant: NANONEX CORPORATION
    Inventors: Wei Zhang, Hua Tan, Stephen Y. Chou
  • Publication number: 20100247698
    Abstract: A mold for imprinting a patterned region by imprint lithography is provided with a peripheral groove around the patterned region. The groove is connected, as by channels through the mold, to a switchable source for gas removal to prevent bubbles and for the application of pressurized gas to separate the mold and substrate. In use, the mold is disposed adjacent the moldable surface and gas is withdrawn from the patterned region through the groove as the mold is pressed toward and into the moldable surface. At or near the end of the imprinting, the process is switched from removal of gas to the application of pressurized gas. The pressurized gas passes through the groove and separates or facilitates separation of the mold and the moldable surface.
    Type: Application
    Filed: June 7, 2010
    Publication date: September 30, 2010
    Applicant: NANONEX CORPORATION
    Inventors: Wei Zhang, Hua Tan, Stephen Y. Chou