Patents by Inventor Hua Wang

Hua Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12389444
    Abstract: A base station may instruct a UE to use at least one weighting factor associated with a CR for the UE, and the UE may apply the at least one weighting factor to the one or more resources scheduled for the PSSCH transmission to determine the CR. The UE may transmit the PSSCH in the one or more resources of the at least one slot based on the determined CR being less than or equal to a CR threshold value. The at least one weighting factor may be applied to the one or more resources in each of multiple slots scheduled for transmission of a PSSCH.
    Type: Grant
    Filed: April 2, 2024
    Date of Patent: August 12, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Hua Wang, Sony Akkarakaran, Jung Ho Ryu, Tao Luo, Junyi Li
  • Publication number: 20250253291
    Abstract: A method for forming a chip package structure. The method includes dicing a semiconductor wafer from a rear surface of the semiconductor wafer to form first and second semiconductor dies. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die after the semiconductor wafer. The method also includes mounting first and second semiconductor dies over an interposer substrate. The first sidewall faces the second sidewall. A lateral distance from a top end of the first sidewall to a top end of the second sidewall is greater than a lateral distance from a bottom end of the first sidewall to a bottom end of the second sidewall.
    Type: Application
    Filed: April 22, 2025
    Publication date: August 7, 2025
    Inventors: Chin-Hua WANG, Shin-Puu JENG, Po-Yao LIN, Po-Chen LAI, Shu-Shen YEH, Ming-Chih YEW, Yu-Sheng LIN
  • Patent number: 12374636
    Abstract: A semiconductor device package is provided, including a substrate, a semiconductor device, a ring structure, a lid structure, and at least one adhesive member. The semiconductor device is disposed over the substrate. The ring structure is disposed over the substrate and surrounds the semiconductor device. The ring structure comprises a first ring part and a second ring part on opposite sides of the semiconductor device. A first gap is formed between the first ring part and the semiconductor device, a second gap is formed between the second ring part and the semiconductor device, and the first gap is smaller than the second gap. The lid structure is disposed over the ring structure and extends across the semiconductor device. The adhesive member is disposed in the first gap and configured to connect the lid structure and the first surface of the substrate.
    Type: Grant
    Filed: January 31, 2024
    Date of Patent: July 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Shen Yeh, Chin-Hua Wang, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 12376342
    Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.
    Type: Grant
    Filed: February 16, 2024
    Date of Patent: July 29, 2025
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Arnab Sen Gupta, Travis W. LaJoie, Sarah Atanasov, Chieh-Jen Ku, Bernhard Sell, Noriyuki Sato, Van Le, Matthew Metz, Hui Jae Yoo, Pei-Hua Wang
  • Patent number: 12374561
    Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip package over the wiring substrate. The chip package structure includes a first heat conductive structure over the chip package. The chip package structure includes a ring dam over the chip package and surrounding the first heat conductive structure. The ring dam has a gap. The chip package structure includes a heat dissipation lid over the first heat conductive structure and the ring dam.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: July 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Sheng Lin, Po-Yao Lin, Shu-Shen Yeh, Chin-Hua Wang, Shin-Puu Jeng
  • Publication number: 20250237675
    Abstract: A jig and a method for grinding probe pins of a probe card. The jig includes a carrier and a connecting part. The carrier carries a support body with a grinding sheet, and the carrier includes an opening. The support body with the grinding sheet straddles above the opening. The opening may expose a plurality of probe pins of the probe card.
    Type: Application
    Filed: February 4, 2024
    Publication date: July 24, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Yi-Fang Ting, Chiu Hua Wang, Cheng Hui Tu
  • Patent number: 12369184
    Abstract: Some aspects described herein relate to receiving a configuration defining resources for transmitting a first message in a two-step random access procedure, wherein the first message includes a random access preamble and a payload, generating a beacon signal for transmitting as the first message, where the beacon signal includes one or more parameters to facilitate discovery by other UEs for pairing in sidelink communications, and transmitting, based on the configuration, the beacon signal as the first message over the resources.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: July 22, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Yisheng Xue, Xiaoxia Zhang, Aleksandar Damnjanovic, Jing Sun, Piyush Gupta, Hua Wang
  • Patent number: 12363653
    Abstract: Certain aspects of the present disclosure provide techniques for configuring sidelink slots with multiple automatic gain control symbols. One aspect provides a method for wireless communication by a user equipment, including enabling a slot configuration comprising at least two symbols configured for use by a receiver for automatic gain control in preconfigured symbol locations within a slot, and transmitting the at least two symbols while transmitting symbols within the slot.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: July 15, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Jung Ho Ryu, Sony Akkarakaran, Tao Luo, Junyi Li, Peter Gaal, Juan Montojo, Xiaoxia Zhang, Xiaojie Wang, Hua Wang, Wooseok Nam, Yan Zhou, Piyush Gupta, Kobi Ravid, Lik Hang Silas Fong, Chih-Hao Liu, Jing Sun
  • Patent number: 12362268
    Abstract: A package assembly includes a package substrate, a solder resist layer on the package substrate and including an elongated solder resist opening, and an interposer module on the package substrate and including a corner located on the elongated solder resist opening.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: July 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Zeng
  • Patent number: 12360464
    Abstract: A lithography system includes a table body, a wafer stage, a first sliding member, a second sliding member, a first cable, a first bracket, a rail guide, and a first protective film. The first sliding member is coupled to the wafer stage. The second sliding member is coupled to an edge of the table body, in which the first sliding member is coupled to a track of the second sliding member. The first bracket fixes the first cable, the first bracket being coupled to a roller structure, in which the roller structure includes a body and a wheel coupled to the body. The rail guide confines a movement of the wheel of the roller structure. The first protective film is adhered to a surface of the rail guide, in which the roller structure is moveable along the first protective film on the surface of the rail guide.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: July 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Hua Wang, Chueh-Chi Kuo, Kuei-Lin Ho, Zong-You Yang, Cheng-Wei Sun, Wei-Yuan Chen, Cheng-Chieh Chen, Heng-Hsin Liu, Li-Jui Chen
  • Patent number: 12356371
    Abstract: Methods, systems, and devices for wireless communications are described. A first user equipment (UE) may receive control signaling indicating a set of component carriers allocated for sidelink communications performed by the first UE. The first UE may receive a message indicating a subset of component carriers from the set of component carriers for use in communicating via a sidelink between the first UE and a second UE, where the subset of component carriers may be supported by the first UE and the second UE. In some cases, a base station or anchor UE may determine or configure the subset of component carriers for use between the first and second UEs. In some cases, the first UE, the second UE, or a both may determine the subset of component carriers. The first UE may communicate with the second UE via a component carrier from the subset of component carriers.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: July 8, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Hua Wang, Sony Akkarakaran, Tao Luo, Junyi Li, Yan Zhou, Hong Cheng, Jelena Damnjanovic, Peter Gaal, Jung Ho Ryu, Qing Li, Juan Montojo
  • Patent number: 12356414
    Abstract: Aspects of the present disclosure provide apparatus, methods, processing systems, and computer-readable mediums for determining timing advances (TAs) for use in sidelink (SL) communications. A method that may be performed by a receiver (RX) user equipment (UE) includes receiving, from a network entity, an indication of a TA for SL communications with a first transmitter (TX) UE and applying the indicated TA when receiving at least one SL transmission from the first TX UE.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: July 8, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Shuanshuan Wu, Kapil Gulati, Hua Wang, Sony Akkarakaran
  • Patent number: 12356337
    Abstract: A method of wireless communication performed at a user equipment (UE) includes receiving, at the UE, a set of downlink (DL) reference signals (RSs) associated with one or more first transmission beams. The method also includes measuring, at the UE, the set of DL-RSs. The method further includes performing, at the UE, an uplink transmission having a transmission power that is set by a pathloss estimation function based on a set of pathloss parameters. One or more of pathloss parameters of the set of pathloss parameters is based on measuring the set of DL-RSs.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: July 8, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Tianyang Bai, Hua Wang, Junyi Li
  • Publication number: 20250220451
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a repeater device may communicate with a user equipment (UE) using a first beam, the communicating comprising relaying an access link communication between the UE and a network node. The repeater device may use a second beam that is predicted by the repeater device to communicate with the UE, the second beam being based at least in part on a network operating condition. Numerous other aspects are described.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Inventors: Tianyang BAI, Hua WANG, Navid ABEDINI, Junyi LI
  • Patent number: 12347793
    Abstract: A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.
    Type: Grant
    Filed: November 23, 2023
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 12345150
    Abstract: A reverse time migration imaging method for cased-hole based on ultrasonic pitch-catch measurement, including: calculating a theoretical dispersion curve; expanding original Lamb data of two receivers into array waveform data based on phase-shift interpolation; establishing a two-dimensional migration velocity model including density, P-wave velocity and S-wave velocity of a target area; generating and storing a forward propagating ultrasonic wavefield for each time step; reversing a time axis; generating and storing a reversely propagating ultrasonic Lamb wavefield for the two receivers after phase-shift interpolation; calculating envelopes of the forward propagating ultrasonic Lamb wavefield and the reversely propagating ultrasonic Lamb wavefield; applying a zero-lag cross-correlation imaging condition to obtain reverse time migration imaging results; and applying Laplace filtering to suppress low-frequency imaging noises in the imaging results.
    Type: Grant
    Filed: October 9, 2022
    Date of Patent: July 1, 2025
    Assignee: University of Electronic Science and Technology of China
    Inventors: Hua Wang, Meng Li
  • Publication number: 20250204652
    Abstract: An extensible lock pull includes: a pull main body including, at one end thereof, a slider connecting portion; a lock head; and a position limiting buffer member. The pull main body is provided with a sliding groove extending along a length direction thereof. The lock head is movably connected to the sliding groove along an extending direction of the sliding groove. The pull main body is provided with an attachment opening portion in communication with the sliding groove at an end of the sliding groove. The lock head is connected to the sliding groove through the attachment opening portion. The position limiting buffer member is fixed to the pull main body and blocks the attachment opening portion. The pull main body and the lock head are both metal parts. The position limiting buffer member is a plastic part or a rubber part.
    Type: Application
    Filed: December 17, 2024
    Publication date: June 26, 2025
    Inventors: Lifeng Chen, Chin Wen Yen, Wei Chen Yeh, Hua Wang
  • Publication number: 20250211321
    Abstract: Methods, systems, and devices for wireless communications are described. The described techniques provide for a network entity obtaining, from a repeater device, an indication of an uplink gain factor associated with uplink transmissions from a user equipment (UE). The network entity may select a precoding matrix associated with downlink transmissions to the UE according to the uplink gain factor. The network entity may output downlink signaling to the UE via the repeater device according to the precoding matrix, a channel rank, and a modulation and coding scheme (MCS) via the repeater device.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Inventors: Hua WANG, Arumugam CHENDAMARAI KANNAN, Divyansh KAREMORE, Navid ABEDINI, Tao LUO, Junyi LI
  • Publication number: 20250210543
    Abstract: A chip package structure is provided. The chip package structure includes a molding compound layer on an interposer substrate. The chip package structure also includes a first semiconductor die over the interposer substrate and surrounded by the molding compound layer. The chip package structure further includes a warpage release layer structure. The warpage release layer structure includes a first organic material layer on the first semiconductor die and the molding compound layer. The warpage release layer structure also includes a first metal layer over the first organic material layer. The first metal layer exposes a portion of a top surface of the first organic material layer.
    Type: Application
    Filed: March 10, 2025
    Publication date: June 26, 2025
    Inventors: Chin-Hua WANG, Kuang-Chun LEE, Shu-Shen YEH, Tsung-Yen LEE, Po-Yao LIN, Shin-Puu JENG
  • Patent number: D1083257
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: July 8, 2025
    Inventors: Hua Wang, Zhongchu Feng, Liye Zhou