Patents by Inventor HUA-WEI TSENG
HUA-WEI TSENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10879224Abstract: A package structure, a die and method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a conductive terminal. The die has a connector. The connector includes a seed layer and a conductive on the seed layer. The seed layer extends beyond a sidewall of the conductive pillar. The encapsulant is aside the die and encapsulates sidewalls of the die. The RDL structure is electrically connected to the die. The conductive terminal is electrically connected to the die through the RDL structure.Type: GrantFiled: January 29, 2019Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Li-Hsien Huang, Ming-Shih Yeh
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Publication number: 20200381373Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.Type: ApplicationFiled: May 31, 2019Publication date: December 3, 2020Inventors: Wan-Yu Lee, Chiang Lin, Yueh-Ting Lin, Hua-Wei Tseng, Li-Hsien Huang, Yu-Hsiang Hu
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Patent number: 10756037Abstract: A package structure including a semiconductor die, an insulating encapsulant, a redistribution layer and a plurality of conductive terminals is provided. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads and a plurality of conductive strips. The conductive pads are disposed on and connected to the plurality of conductive pads, wherein each of the conductive strips is physically connected to at least two conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant and the semiconductor die, wherein the redistribution layer is electrically connected to the plurality of conductive strips. The plurality of conductive terminals is disposed on the redistribution layer.Type: GrantFiled: May 15, 2018Date of Patent: August 25, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsien Huang, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Yueh-Ting Lin, Ming-Shih Yeh
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Publication number: 20200135708Abstract: A package structure, a die and method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a conductive terminal. The die has a connector. The connector includes a seed layer and a conductive on the seed layer. The seed layer extends beyond a sidewall of the conductive pillar. The encapsulant is aside the die and encapsulates sidewalls of the die. The RDL structure is electrically connected to the die. The conductive terminal is electrically connected to the die through the RDL structure.Type: ApplicationFiled: January 29, 2019Publication date: April 30, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Li-Hsien Huang, Ming-Shih Yeh
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Patent number: 10541226Abstract: An embodiment is a structure including a first die, a molding compound at least laterally encapsulating the first die, a first redistribution structure including metallization patterns extending over the first die and the molding compound, a first conductive connector comprising a solder ball and an under bump metallization coupled to the first redistribution structure, and an integrated passive device bonded to a first metallization pattern in the first redistribution structure with a micro bump bonding joint, the integrated passive device being adjacent the first conductive connector.Type: GrantFiled: October 3, 2016Date of Patent: January 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, An-Jhih Su, Hua-Wei Tseng
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Publication number: 20190371718Abstract: A method for manufacturing a semiconductor device includes following operations. A first substrate with a conductive pad is received. A connector is disposed over the conductive pad. A second substrate including a conductive land is provided. A position of the first substrate or the second substrate is adjusted thereby a geometric center of the conductive land is deviated from a geometric center of the connector in a deviated distance. The connector is bonded with the conductive land. A temperature of the semiconductor device is adjusted so as to control elongation of the first substrate and the second substrate, thereby the geometric center of the connector is substantially aligned with the geometric center of the conductive land.Type: ApplicationFiled: August 13, 2019Publication date: December 5, 2019Inventors: HUA-WEI TSENG, CHITA CHUANG, MING HUNG TSENG, CHEN-SHIEN CHEN, MIRNG-JI LII
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Publication number: 20190355687Abstract: A package structure including a semiconductor die, an insulating encapsulant, a redistribution layer and a plurality of conductive terminals is provided. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads and a plurality of conductive strips. The conductive pads are disposed on and connected to the plurality of conductive pads, wherein each of the conductive strips is physically connected to at least two conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant and the semiconductor die, wherein the redistribution layer is electrically connected to the plurality of conductive strips. The plurality of conductive terminals is disposed on the redistribution layer.Type: ApplicationFiled: May 15, 2018Publication date: November 21, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsien Huang, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Yueh-Ting Lin, Ming-Shih Yeh
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Publication number: 20190348353Abstract: A redistribution structure includes a first dielectric layer and a first redistribution circuit layer. The first dielectric layer includes a first via opening. The first redistribution circuit layer is disposed on the first dielectric layer and includes a via portion filling the first via opening and a circuit portion connecting the via portion and extending over the first dielectric layer. A maximum vertical distance between an upper surface of the via portion and an upper surface of the circuit portion is substantially equal to or smaller than 0.5 ?m.Type: ApplicationFiled: August 7, 2018Publication date: November 14, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsien Huang, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Chiang Lin, Ming-Shih Yeh
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Patent number: 10290610Abstract: A PoP device includes a first package structure, a second package structure and an underfill layer is provided. The first package structure includes a die, a TIV and an encapsulant. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and a portion of sidewalls of the TIV. The second package structure is connected to the first package structure through a connector. The underfill layer is disposed to fill a space between the first package structure and the second package structure. A portion of the underfill layer is disposed between the encapsulant and the TIV to cover a portion of sidewalls of the TIV.Type: GrantFiled: August 29, 2017Date of Patent: May 14, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsien Huang, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Li-Hui Cheng, Po-Hao Tsai, Wei-Yu Chen, Ming-Shih Yeh
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Patent number: 10276542Abstract: A package structure has first and second dies, a molding compound, a first redistribution layer, at least one first through interlayer via (TIV), second through interlayer vias (TIVs), an electromagnetic interference shielding layer and conductive elements. The first die is molded in the molding compound. The second die is disposed on the molding compound. The first redistribution layer is located between the conductive elements and the molding compound and electrically connected to the first and second dies. The molding compound is located between the second die and the first redistribution layer. The first and second TIVs are molded in the molding compound and electrically connected to the first redistribution layer. The second TIVs are located between the first die and the first TIV. The electromagnetic interference shielding layer is in contact with the first TIV. The conductive elements are connected to the first redistribution layer.Type: GrantFiled: July 21, 2016Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen, Hua-Wei Tseng, Jo-Mei Wang, Tien-Chung Yang, Kuan-Chung Lu
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Publication number: 20190067249Abstract: A PoP device includes a first package structure, a second package structure and an underfill layer is provided. The first package structure includes a die, a TIV and an encapsulant. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and a portion of sidewalls of the TIV. The second package structure is connected to the first package structure through a connector. The underfill layer is disposed to fill a space between the first package structure and the second package structure. A portion of the underfill layer is disposed between the encapsulant and the TIV to cover a portion of sidewalls of the TIV.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsien Huang, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Li-Hui Cheng, Po-Hao Tsai, Wei-Yu Chen, Ming-Shih Yeh
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Publication number: 20190035772Abstract: A semiconductor package includes a die, an insulation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The insulation layer is disposed on the die and includes a plurality of openings exposing the first pads and the second pads. The first electrical conductive vias and the second electrical conductive vias are disposed in the openings and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the insulation layer. The connecting pattern is disposed on the insulation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.Type: ApplicationFiled: July 27, 2017Publication date: January 31, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsien Huang, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hua-Wei Tseng, Ming-Chih Yew, Yi-Jen Lai, Ming-Shih Yeh
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Publication number: 20180331069Abstract: An embodiment is a structure including a first die, a molding compound at least laterally encapsulating the first die, a first redistribution structure including metallization patterns extending over the first die and the molding compound, a first conductive connector comprising a solder ball and an under bump metallization coupled to the first redistribution structure, and an integrated passive device bonded to a first metallization pattern in the first redistribution structure with a micro bump bonding joint, the integrated passive device being adjacent the first conductive connector.Type: ApplicationFiled: July 24, 2018Publication date: November 15, 2018Inventors: Chen-Hua Yu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, An-Jhih Su, Hua-Wei Tseng
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Patent number: 10037973Abstract: A method for manufacturing a semiconductor package structure is provided. A semiconductor substrate comprising a conductive pad is provided, wherein the conductive pad is coupled with a circuitry of the semiconductor substrate. A patterned passivation layer exposing a portion of the conductive pad is formed. An uneven surface of the conductive pad is formed. A photoresist is formed on the semiconductor substrate. The photoresist is exposed under a light beam, wherein the light beam is scattered by the uneven surface. The photoresist is developed to form an opening in the photoresist so as to expose the conductive pad and form a plurality of cavities in the remaining photoresist. A conductive material is formed in the opening and the plurality of cavities.Type: GrantFiled: July 15, 2016Date of Patent: July 31, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hua-Wei Tseng, Shang-Yun Tu, Hsu-Hsien Chen, Hao-Juin Liu, Chen-Shien Chen, Ming Hung Tseng, Chita Chuang
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Publication number: 20180033771Abstract: An embodiment is a structure including a first die, a molding compound at least laterally encapsulating the first die, a first redistribution structure including metallization patterns extending over the first die and the molding compound, a first conductive connector comprising a solder ball and an under bump metallization coupled to the first redistribution structure, and an integrated passive device bonded to a first metallization pattern in the first redistribution structure with a micro bump bonding joint, the integrated passive device being adjacent the first conductive connector.Type: ApplicationFiled: October 3, 2016Publication date: February 1, 2018Inventors: Chen-Hua Yu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, An-Jhih Su, Hua-Wei Tseng
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Publication number: 20180026010Abstract: A package structure has first and second dies, a molding compound, a first redistribution layer, at least one first through interlayer via (TIV), second through interlayer vias (TIVs), an electromagnetic interference shielding layer and conductive elements. The first die is molded in the molding compound. The second die is disposed on the molding compound. The first redistribution layer is located between the conductive elements and the molding compound and electrically connected to the first and second dies. The molding compound is located between the second die and the first redistribution layer. The first and second TIVs are molded in the molding compound and electrically connected to the first redistribution layer. The second TIVs are located between the first die and the first TIV. The electromagnetic interference shielding layer is in contact with the first TIV. The conductive elements are connected to the first redistribution layer.Type: ApplicationFiled: July 21, 2016Publication date: January 25, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen, Hua-Wei Tseng, Jo-Mei Wang, Tien-Chung Yang, Kuan-Chung Lu
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Patent number: 9793246Abstract: PoP devices and methods of forming the same are disclosed. A PoP device includes a first package structure and a second package structure. The first package structure includes a first chip, and a plurality of active through integrated fan-out vias and a plurality of dummy through integrated fan-out vias aside the first chip. The second package structure includes a plurality active bumps bonded to the plurality of active through integrated fan-out vias, and a plurality of dummy bumps bonded to the plurality of dummy through integrated fan-out vias. Besides, a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a first side of the first chip is substantially the same as a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a second side of the first chip.Type: GrantFiled: July 21, 2016Date of Patent: October 17, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hua-Wei Tseng, An-Jhih Su, Hsien-Wei Chen, Li-Hsien Huang, Tien-Chung Yang
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Publication number: 20160336298Abstract: A method for manufacturing a semiconductor package structure is provided. A semiconductor substrate comprising a conductive pad is provided, wherein the conductive pad is coupled with a circuitry of the semiconductor substrate. A patterned passivation layer exposing a portion of the conductive pad is formed. An uneven surface of the conductive pad is formed. A photoresist is formed on the semiconductor substrate. The photoresist is exposed under a light beam, wherein the light beam is scattered by the uneven surface. The photoresist is developed to form an opening in the photoresist so as to expose the conductive pad and form a plurality of cavities in the remaining photoresist. A conductive material is formed in the opening and the plurality of cavities.Type: ApplicationFiled: July 15, 2016Publication date: November 17, 2016Inventors: HUA-WEI TSENG, SHANG-YUN TU, HSU-HSIEN CHEN, HAO-JUIN LIU, CHEN-SHIEN CHEN, MING HUNG TSENG, CHITA CHUANG
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Patent number: 9406629Abstract: A semiconductor package structure includes a first semiconductor substrate including a conductive pad; and a conductive pillar on the conductive pad and disposed between the first semiconductor substrate and a second semiconductor substrate. The conductive pad is coupled with a circuitry of the first semiconductor substrate. The conductive pillar extends along a longitudinal axis and toward the second semiconductor substrate. The conductive pillar includes a sidewall with a rough surface notching toward the longitudinal axis.Type: GrantFiled: October 15, 2014Date of Patent: August 2, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hua-Wei Tseng, Shang-Yun Tu, Hsu-Hsien Chen, Hao-Juin Liu, Chen-Shien Chen, Ming Hung Tseng, Chita Chuang
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Publication number: 20160111384Abstract: A semiconductor package structure includes a first semiconductor substrate including a conductive pad; and a conductive pillar on the conductive pad and disposed between the first semiconductor substrate and a second semiconductor substrate. The conductive pad is coupled with a circuitry of the first semiconductor substrate. The conductive pillar extends along a longitudinal axis and toward the second semiconductor substrate. The conductive pillar includes a sidewall with a rough surface notching toward the longitudinal axis.Type: ApplicationFiled: October 15, 2014Publication date: April 21, 2016Inventors: HUA-WEI TSENG, SHANG-YUN TU, HSU-HSIEN CHEN, HAO-JUIN LIU, CHEN-SHIEN CHEN, MING HUNG TSENG, CHITA CHUANG