Abstract: A manufacturing system includes a substrate disposed on a conveyer system. The conveyer system includes a pair of side supports. The substrate is moved on the conveyer system until the substrate is disposed over a bottom support block. The bottom support block is raised to physically contact the substrate. A transfer arm module is provided. The transfer arm module includes a flat bottom surface and an opening formed in the flat bottom surface. The transfer arm module is disposed with the flat bottom surface physically contacting the substrate opposite the bottom support block. A vacuum is enabled through the opening of the transfer arm module. The substrate is lifted off the bottom support block using the vacuum. The substrate is moved over a printing pallet using the transfer arm module. The vacuum is disabled when the substrate is in a positioning area of the printing pallet.

Abstract: A method for determining a consistency coefficient of a power-law cement grout includes: determining a water-cement ratio of the power-law cement grout; according to engineering practice requirements, determining a time required to determine the consistency coefficient of the power-law cement grout; and obtaining the consistency coefficient of the power-law cement grout. The method is accurate and reliable, requires less calculation, etc.; and has very high practical value and popularization value in environmental protection and ecological restoration.

Abstract: A semiconductor manufacturing equipment cleaning system has a multi-station cleaning and inspection system. Within semiconductor manufacturing equipment cleaning system, a tray cleaning station uses a first rotating brush passing over a first surface of a carrier and possibly semiconductor die, and a second rotating brush passing over a second surface of the carrier and semiconductor die opposite the first surface of the carrier and semiconductor die. Debris and contaminants dislodged from the first surface and second surface of the carrier by the first rotating brush and second rotating brush are removed under vacuum suction. A conveyor transports the carrier through the multi-station cleaning and inspection system. The first rotating brush and second rotating brush move in tandem across the first surface and second surface of the carrier. Air pressure is injected across the first rotating brush and second rotating brush to further remove debris and contaminants.

Abstract: A method for determining a three-dimensional tortuosity of a loose and broken rock-soil mass, includes the following steps: a particle grading curve of the loose and broken rock-soil mass is obtained by utilizing a particle size analysis, and followed by calculating an equivalent particle size and an average particle size; a porosity of the loose and broken rock-soil mass is obtained by utilizing a moisture content test, a density test, and a specific gravity test; the three-dimensional tortuosity of the loose and broken rock-soil mass is obtained by utilizing the equivalent particle size, the average particle size and the porosity of the loose and broken rock-soil mass. The method has the advantages of simple logic, accuracy and reliability, simple and fast parameter determination, and has high practical value and promotion value in the field of environmental protection and ecological restoration technology.

Abstract: A method, system, and computer program product for bit flip aware latch placement in integrated circuit generation are provided. The method identifies a chip design for an integrated circuit. A set of chip design constraints, associated with the chip design, is identified. A set of checking groups, associated with a plurality of latches to be placed in the chip design, is determined. Based on the set of chip design constraints and the set of checking groups, a placement scheme for the plurality of latches is selected. The method places the plurality of latches within the chip design based on the placement scheme and the set of checking groups.

Abstract: Disclosed herein are methods, systems, compositions and strategies for the creation and use WW-domain-Activated Extracellular Vesicles (WAEVs) for presenting HIV antigen domains. These WAEVs can be harnessed to deliver and present HIV antigens useful for vaccine development. Specifically, the disclosure provides a fusion protein comprising: (a) a WW-containing domain; (b) a transmembrane domain; and (c) an extracellular domain, wherein the extracellular domain is an HIV antigen domain. Further provided are sequences of each domain as well as methods of producing and using the fusion protein.

Abstract: Disclosed is a split continuous operation micro-grid dynamic membrane bioreactor. The split continuous operation micro-grid dynamic membrane bioreactor comprises a biological treatment unit and a drum dynamic membrane filtration unit, wherein the biological treatment unit comprises a microbiological treatment tank, and a water inlet pipe is arranged on the microbiological treatment tank; the drum dynamic membrane filtration unit comprises a filter tank, and a drum micro-grid dynamic membrane mechanism is arranged in the filter tank; the drum micro-grid dynamic membrane mechanism comprises a filter drum, a backwashing device is arranged above the filter drum, and a sludge collecting tank is arranged in the filter drum; a water outlet is formed in the bottom of the filter tank; a mixed liquid pipe is arranged between the microbiological treatment tank and the filter drum; and a sludge discharge header pipe is arranged on the sludge collecting tank.

Abstract: Embodiments are provided for providing enhanced routing in a computing system by a processor. One or more of a plurality of short nets in a cell of an integrated circuit may be aligned for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold.

Abstract: Design rule violations (“DRVs”) may be predicted using a design rule check (“DRC”) density map during a physical synthesis operation prior to executing a routing operation.

Abstract: Embodiments are provided for providing power staple avoidance during routing in a computing system by a processor. One or more transistor gates may be shifted in each row of an integrated circuit to avoid alignment of cell pins and power staples for executing a routing operation, where the circuit row is partitioned into segments based on one or more fixed objects.

Abstract: Techniques regarding parameter tuning for an EDA protocol are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a tuning component that tunes an electronic design automation protocol via a cooperative co-evolutionary optimization framework that shares parameter knowledge across multiple stages of the electronic design automation protocol.

Abstract: A method for patterning a stack having a mask with a plurality of mask features is provided. A targeted deposition is provided, wherein the targeted deposition comprises a plurality of cycles, wherein each cycle comprises flowing a precursor to deposit a layer of precursor and targeted curing the layer of precursor, comprising flowing a curing gas, flowing a modification gas, forming a plasma from the curing gas and modification gas, and exposing the layer of precursor to the plasma providing a targeted curing, wherein plasma from the curing gas cures first portions of the layer of precursor and plasma from the modification gas modifies second portions of the layer of precursor, wherein the modification of the second portion reduces curing of the layer of precursor of the second portions of the layer of precursor. The stack is etched through the targeted deposition.

Abstract: The present application provides a method for improving colour difference of an LED display screen, comprising: drilling and polishing circuit surfaces of a plurality of LED substrates; performing screen printing on the circuit surfaces of the plurality of LED substrates, and performing oil skimming on a mesh screen during the screen printing every other preset printing cycle in such a way that an ink on the mesh screen has a viscosity within a predetermined viscosity range; performing an exposure setting process on the plurality of LED substrates that have been screen printed to obtain a plurality of LED printed circuit boards; and finally assembling the plurality of LED printed circuit boards to form an LED display screen.

Abstract: Provided herein are methods and related apparatus for mask reconstruction in an etch process. The methods involve depositing a sacrificial layer on the mask layer. The sacrificial layer may be used to protect position on the mask layer. Following mask reshaping, the sacrificial layer may be removed using the same etch process that is used to etch the target material.

Abstract: Disclosed is a split type continuous operation micro-grid dynamic membrane bioreactor. The split type continuous operation micro-grid dynamic membrane bioreactor comprises a biological treatment unit and a drum type dynamic membrane filtration unit, wherein the biological treatment unit comprises a microbiological treatment tank, and a water inlet pipe is arranged on the microbiological treatment tank; the drum type dynamic membrane filtration unit comprises a filter tank, and a drum micro-grid dynamic membrane mechanism is arranged in the filter tank; the drum micro-grid dynamic membrane mechanism comprises a filter drum, a backwashing device is arranged above the filter drum, and a sludge collecting bank is arranged in the filter drum; a water outlet is formed in the bottom of the filter tank; a mixed liquid pipe is arranged between the microbiological treatment tank and the filter drum; and a sludge discharge header pipe is arranged on the sludge collecting tank.

Abstract: This document relates to methods and materials for treating a mammal having a Zika virus (ZIKV) infection.

Abstract: A method for enhancing routability in a cell-based design includes: obtaining a layout corresponding to a placement of cells in the cell-based design; identifying one or more areas of the layout where routability is predicted to be constrained; selectively adding white spaces to the identified one or more areas of the layout where routability is predicted to be constrained to thereby generate a modified layout; legalizing placement of the modified layout; and running a detailed routing on the modified layout.

Abstract: Techniques for dynamically generating self-aligned double patterning (SADP) gate regions based on gate distribution and the relocation of the gates to their matched region are provided. In one aspect, a method for generating SADP gate regions in a circuit design includes: obtaining a circuit design having SADP gates, and a placement solution for the SADP gates that, while non-overlapping, violates SADP track routing matching requirements; determining approximate locations of SADP regions in the circuit design; assigning the SADP gates to the SADP regions using a minimum-cost maximum-flow (min-cost max-flow) process; and identifying, once all of the SADP gates have been assigned to the SADP regions, non-overlapping locations for the SADP gates in the SADP regions.

Abstract: This document relates to methods and materials for treating a mammal having a Zika virus (ZIKV) infection.

Abstract: Techniques regarding functional placement of one or more logic gates in a periodic circuit row configuration are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an optimization component, operatively coupled to the processor, that can determine functional placement of a logic gate in a self-aligned double patterning process that can form a periodic circuit row configuration.