Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: A chip card ejecting mechanism includes a base body, a push member, a rotating member and an elastic member resisting between the base body and the rotating member. The base body includes a guiding member defining a hole and having a number of guiding rails. Each guiding rail includes a resisting surface and a guiding surface. The push member includes a push rod extending through the hole and a number of active gears. Each active gear defines an active cooperative surface. The rotating member includes a number of the passive gears. Each passive gear includes a passive cooperative surface. When the push member is pressed toward the rotating member by a transient external force, the rotating member compresses the elastic member until the active cooperative surface arrives at the guiding surface, the elastic member releases and drives the passive cooperative gears to slide along the first sliding slot.

Abstract: The present disclosure relates to a computer-based method and apparatus for determining datapath bit slices. A first two-way search is performed between an input vector and an output vector to identify gates in a datapath. A network flow is then constructed including the gates identified, and a min-cost max-flow algorithm is applied to the network flow to derive matching bit pairs between the input vector and the output vector. Next, the datapath bit slices are determined by performing a second two-way search between each of a starting bit in the input vector and an ending bit in the output vector of each of the matching bit pairs.

Abstract: Systems and methods for relative ordering circuit synthesis are provided herein. One aspect provides for generating at least one circuit design via at least one processor accessible by a computing device; wherein generating at least one circuit design comprises: generating at least one relative order structure based on at least one circuit design layout, the at least one relative order structure comprising at least one placement constraint associated with at least one circuit element; placing the at least one circuit element associated with the at least one placement constraint within a circuit design according to the at least one placement constraint; and placing circuit elements not associated with the at least one placement constraint within the circuit design. Other embodiments and aspects are also described herein.

Abstract: In one embodiment, the invention is a method and apparatus for soft hierarchy-based synthesis for large-scale, high-performance circuits. One embodiment of a method for physically synthesizing a design of an integrated circuit includes compiling a logical description of the design into a flattened netlist, extracting a soft hierarchy from the flattened netlist, wherein the soft hierarchy defines a boundary on a die across which cells of the integrated circuit are permitted to move, and placing a cell of the integrated circuit on the die in accordance with the soft hierarchy.

Abstract: Latches and local-clock-buffers are automatically placed during integrated circuit physical synthesis. Prior to physically laying out the datapath, locations are assigned for the latches based on a logical representation of the datapath and on the fixed placements of pins. The computed latch locations optimize the datapath according to some predetermined criteria. Local-clock-buffers are also preplaced together with the latches further improving datapath performance.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: A protective case includes a main body having a recess and a flange in the recess, a strengthening plate received in the recess. The strengthening plate includes a latching block. The latching block is latched with the flange to latch the strengthening plate in the recess. When the case is used to protect an electronic device, the strengthening plate shield the electronic device from damaging.

Abstract: The present disclosure relates to a computer-based method and apparatus for determining datapath bit slices. A first two-way search is performed between an input vector and an output vector to identify gates in a datapath. A network flow is then constructed including the gates identified, and a min-cost max-flow algorithm is applied to the network flow to derive matching bit pairs between the input vector and the output vector. Next, the datapath bit slices are determined by performing a second two-way search between each of a starting bit in the input vector and an ending bit in the output vector of each of the matching bit pairs.

Abstract: Indenoisoquinolinone derivatives (I), the manufacturing method and the medical use thereof, which belong to pharmaceutical chemistry and organic chemistry field, are disclosed. These compounds can be used for treating several medical symptoms related to postmenopausal syndrome, uterine fibers deterioration and aortic smooth muscle cells proliferation, especially ER-(+) depend breast cancer. Meanwhile, these compounds can also be used for treating glioma and lung cancer, and have inhibiting effect on tumor metastasis effect on tumor metastasis.

Abstract: Isoflavone fatty acid ester derivatives of formula (I) or (II), the preparation method thereof and the pharmaceutical compositions containing such compounds are disclosed. The uses of such compounds in preparation of medicaments for preventing or treating hyperlipidemia, obesity or type II diabetes are also disclosed.

Abstract: In one embodiment, the invention is a method and apparatus for soft hierarchy-based synthesis for large-scale, high-performance circuits. One embodiment of a method for physically synthesizing a design of an integrated circuit includes compiling a logical description of the design into a flattened netlist, extracting a soft hierarchy from the flattened netlist, wherein the soft hierarchy defines a boundary on a die across which cells of the integrated circuit are permitted to move, and placing a cell of the integrated circuit on the die in accordance with the soft hierarchy.

Abstract: Stabilized forms of gp120 polypeptide, nucleic acids encoding these stabilized forms, vectors comprising these nucleic acids, and methods of using these polypeptides, nucleic acids, vectors and host cells are disclosed. Crystal structures and computer systems including atomic coordinates for stabilized forms of gp120, and gp120 with an extended V3 loop, and methods of using these structures and computer systems are also disclosed.

Abstract: A light guide module (4) and backlight that incorporates this module are disclosed. In some embodiments, a light guide module includes a light guide (1) having an input surface (11) to receive light. The module also includes a structured surface layer (2) including a first surface (812) and a second surface (13). The first surface (12) is attached to the input surface (11) of the light guide (1). And the second surface (13) includes microstructures (21) that are operable to spread incident light in the plane of the light guide (1). The second surface (13) is positioned to receive light emitted from an array of light emitting diodes (3).

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: Stabilized forms of gp120 polypeptide, nucleic acids encoding these stabilized forms, vectors comprising these nucleic acids, and methods of using these polypeptides, nucleic acids, vectors and host cells are disclosed. Crystal structures and computer systems including atomic coordinates for stabilized forms of gp120, and gp120 with an extended V3 loop, and methods of using these structures and computer systems are also disclosed.

Abstract: Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.

Abstract: A scaled network flow graph is constructed, including a plurality of nodes and a plurality of edges. The plurality of nodes correspond to: (i) a pseudo device pin node for each pair of corresponding paired device pins; (ii) a pseudo bottom surface metal node for each pair of bottom surface metal pins on each of multiple routing layers; (iii) a source node connected to each of the pseudo device pin nodes; (iv) a sub-sink node for each pair of the paired bottom surface metal pins (each of the sub-sink nodes is connected to corresponding ones of the pseudo bottom surface metal nodes for each of the pairs of bottom surface metal pins on each of the multiple routing layers); and (v) a sink node connected to the sub-sink nodes. A capacity and a cost are assigned to each of the edges of the scaled network flow graph. A min-cost-max-flow technique is applied to the scaled network flow graph with the assigned capacities and costs to obtain an optimal flow solution.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: A portable electronic device comprises a housing and a chip card ejecting mechanism. The housing has a mounting portion defined therein. The ejecting mechanism includes a holder and a controlling module. The holder is slidably accommodated in the mounting portion of the housing. The controlling module includes a button and an ejecting element. The button releasably secures with the holder in the mounting portion. The ejecting element resistes against the holder to provide an elastic force for driving the holder slid. When the button is pressed, the holder is released and the ejecting element ejects the holder outwardly from the mounted portion of the housing.