Abstract: Stabilized forms of gp120 polypeptide, nucleic acids encoding these stabilized forms, vectors comprising these nucleic acids, and methods of using these polypeptides, nucleic acids, vectors and host cells are disclosed. Crystal structures and computer systems including atomic coordinates for stabilized forms of gp120, and gp120 with an extended V3 loop, and methods of using these structures and computer systems are also disclosed.

Abstract: A CPU mounting apparatus is disclosed. The CPU mounting apparatus includes a CPU receiver, two lever holders, two clips, two resilient members, a pair of levers, and a handle. The CPU receiver defines a cavity for receiving a CPU. The two clips are slidably mounted between the lever holders and the CPU receiver and include clip ends for holding the CPU. The resilient members apply resilient forces on the clips so that the clips can hold the CPU firmly. The levers are fixed on the lever holders and are positioned between the clips for pushing the clips to move. The handle is mounted on the lever holders above the levers for driving the levers to move. The CPU mounting apparatus is used to load/remove a CPU to/from a socket.

Abstract: A hinge positioning apparatus includes a base, a first positioning unit, and a second positioning unit. The first positioning unit includes a load-supporting platform, a first locking means, and a plurality of limiting blocks. The load-supporting platform is mounted on the base. The first locking means is movable between a loose position and a locking position. The limiting blocks respectively mounted on the load-supporting platform and the first locking means. The second positioning unit includes two coaxial supports and two second locking means. The supports are mounted on the base adjacent the load-supporting platform, each defines a positioning groove in side surface facing the load-supporting platform. The second locking means are mounted on the supports respectively, configured for maintaining hinges in the positioning grooves. The apparatus is used to position two hinges coaxially on an enclosure of a notebook computer.

Abstract: The present invention provides a method of performing BSM assignments for each routing layer typically having one BSM group (e.g. memory bus) per layer. Further, the present invention provides for routable BSM assignments. Further, the present invention provides a method for handling pair constraints providing for differential pairs to be placed close to each other. Further, the method of the present invention provides for simultaneous routing and pin assignments while honoring pair constraint concerns and optimizing wire length.

Abstract: The present disclosure relates to stabilized forms of the HIV gp120 envelope protein in complex with the broadly neutralizing CD4-binding site antibody b12, to crystalline forms of the stabilized forms of the HIV gp120 envelope protein in complex with the broadly neutralizing CD4-binding site antibody b12, and to the high resolution structure obtained from these crystals by X-ray diffraction methods. Methods for identifying immunogenic polypeptides based on these structures are also disclosed.

Abstract: A screwdriver extension includes a supporting plate, a transferring part, a transmission shaft, and a receiving sleeve. The transferring part includes a housing and a plurality of meshed gears mounted in the housing. The supporting plate connects the transferring part to an electric screwdriver. The transmission shaft is driven by the electric screwdriver and drives the gears, which in turn drives the receiving sleeve. The sleeve receives a screwdriver head. The screwdriver extension helps the electric screwdriver to tighten screws along axes of corresponding holes.

Abstract: The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.

Abstract: A screwdriver helper includes a handle, a guide, and a bit. The handle defines a through hole therein. The guide is affixed to the handle. The guide comprises a top surface, a bottom surface, and a through guide hole defined between the top surface and the bottom surface. The top surface is faced to the handle. The guide hole is corresponding to the through hole of the handle. An axis of the guide hole is perpendicular to the bottom surface. The bit is positioned in the guide hole. The bit comprises a tip and a head. The tip is in a shape of a screw head. The head defines slots in a top end thereof. The bit is movable along the axis of the through guide hole. The screwdriver helper helps screwdriver to lock screws firmly.

Abstract: The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.

Abstract: An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.

Abstract: A CPU mounting apparatus is disclosed. The CPU mounting apparatus includes a CPU receiver, two lever holders, two clips, two resilient members, a pair of levers, and a handle. The CPU receiver defines a cavity for receiving a CPU. The two clips are slidably mounted between the lever holders and the CPU receiver and include clip ends for holding the CPU. The resilient members apply resilient forces on the clips so that the clips can hold the CPU firmly. The levers are fixed on the lever holders and are positioned between the clips for pushing the clips to move. The handle is mounted on the lever holders above the levers for driving the levers to move. The CPU mounting apparatus is used to load/remove a CPU to/from a socket.

Abstract: A clamp tool for circuit board is disclosed. The clamp tool includes a frame, a handle, a plurality of gripping shafts, and a locking means. The frame defines two vertical grooves facing to each other. The handle is mounted on top of the frame. The gripping shafts are mounted beneath the frame, and include protuberant gripping heads on an end thereof. The locking means includes a pull rod and a locking shaft. The pull rod passes through the vertical grooves and connects with the frame by elastic pieces. The locking shaft is mounted beneath the pull rod. The clamp tool is used to move circuit boards.

Abstract: An assembling apparatus is disclosed. The assembling apparatus includes a base, an assembling platform, and a driving part. The assembling platform and the driving part are fixed on the base. The assembling platform defines a receiving space for receiving a semiconductor chip module, a lever chamber for receiving clips of the semiconductor chip module, and a driving groove for connecting the receiving space and the lever chamber. The assembling platform further includes a lever bar removably placed in the lever chamber for expanding the clips. The driving part includes driving shafts. An end of each of the driving shafts is in the driving groove and is movable to pass through the lever chamber and reaches the receiving space. The assembling apparatus is used to assemble a semiconductor chip module conveniently and safely.

Abstract: The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.

Abstract: The present invention relates to a low loss boost circuit used in power conversion equipment of power supplies or other power systems. It comprises controlling a duty cycle of a power switch; realizing voltage boosting and regulating of the output voltage through the energy storage in a boost inductor; reducing the reverse recovery current using an auxiliary inductor, wherein a secondary winding of the inductor supplies additional energy thereto and provides a path for transferring the energy from the auxiliary inductor to the energy storage capacitor. The present invention has high efficiency and is suitable for power converter with PFC, such as, telecommunication power supply and uninterrupted power supply.

Abstract: The present invention relates to a low loss boost circuit used in power conversion equipment of power supplies or other power systems. It comprises controlling a duty cycle of a power switch; realizing voltage boosting and regulating of the output voltage through the energy storage in a boost inductor; reducing the reverse recovery current using an auxiliary inductor, wherein a secondary winding of the inductor supplies additional energy thereto and provides a path for transferring the energy from the auxiliary inductor to the energy storage capacitor. The present invention has high efficiency and is suitable for power converter with PFC, such as, telecommunication power supply and uninterrupted power supply.