Patents by Inventor Huai-Tei Yang
Huai-Tei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11854811Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.Type: GrantFiled: April 14, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Min Huang, Huai-Tei Yang, Shih-Chieh Chang
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Publication number: 20230378359Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
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Patent number: 11817499Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: GrantFiled: June 29, 2022Date of Patent: November 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
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Publication number: 20230352533Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.Type: ApplicationFiled: July 12, 2023Publication date: November 2, 2023Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
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Publication number: 20230278160Abstract: A method of using a polishing system includes securing a wafer in a carrier head, the carrier head including a housing enclosing the wafer, in which the housing includes a retainer ring recess and a retainer ring positioned in the retainer ring recess, the retainer ring surrounding the wafer, in which the retainer ring includes a main body portion and a bottom portion connected to the main body portion, and a bottom surface of the bottom portion includes at least one first engraved region and a first non-engraved region adjacent to the first engraved region; pressing the wafer against a polishing pad; and moving the carrier head or the polishing pad relative to the other.Type: ApplicationFiled: May 12, 2023Publication date: September 7, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Yuan YANG, Huai-Tei YANG, Yu-Chen WEI, Szu-Cheng WANG, Li-Hsiang CHAO, Jen-Chieh LAI, Shih-Ho LIN
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Patent number: 11742386Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.Type: GrantFiled: July 25, 2022Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
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Patent number: 11685015Abstract: A method of using a polishing system includes securing a wafer in a carrier head, the carrier head including a housing enclosing the wafer, in which the housing includes a retainer ring recess and a retainer ring positioned in the retainer ring recess, the retainer ring surrounding the wafer, in which the retainer ring includes a main body portion and a bottom portion connected to the main body portion, and a bottom surface of the bottom portion includes at least one first engraved region and a first non-engraved region adjacent to the first engraved region; pressing the wafer against a polishing pad; and moving the carrier head or the polishing pad relative to the other.Type: GrantFiled: January 28, 2019Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Yuan Yang, Huai-Tei Yang, Yu-Chen Wei, Szu-Cheng Wang, Li-Hsiang Chao, Jen-Chieh Lai, Shih-Ho Lin
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Publication number: 20230141521Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: ApplicationFiled: January 2, 2023Publication date: May 11, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu LIN, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
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Publication number: 20230116357Abstract: A method of forming an integrated circuit structure includes forming a gate dielectric on a wafer, forming a work function layer over the gate dielectric, depositing a capping layer over the work function layer, soaking the capping layer in a silicon-containing gas to form a silicon-containing layer, forming a blocking layer after the silicon-containing layer is formed, and forming a metal-filling region over the blocking layer.Type: ApplicationFiled: December 12, 2022Publication date: April 13, 2023Inventors: Chun-Chieh Wang, Yueh-Ching Pai, Kuo-Jung Huang, Huai-Tei Yang
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Publication number: 20230109135Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a S/D silicide layer formed on the S/D epitaxial layer, and the S/D silicide layer has a first width, the S/D epitaxial layer has a second width, and the first width is smaller than the second width. The semiconductor structure includes a dielectric spacer between the gate structure and the S/D silicide layer, and a top surface of the dielectric spacer is lower than a top surface of the gate structure.Type: ApplicationFiled: December 9, 2022Publication date: April 6, 2023Inventors: Chun-Chieh WANG, Yu-Ting LIN, Yueh-Ching PAI, Shih-Chieh CHANG, Huai-Tei YANG
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Patent number: 11587791Abstract: A method of forming an integrated circuit structure includes forming a gate dielectric on a wafer, forming a work function layer over the gate dielectric, depositing a capping layer over the work function layer, soaking the capping layer in a silicon-containing gas to form a silicon-containing layer, forming a blocking layer after the silicon-containing layer is formed, and forming a metal-filling region over the blocking layer.Type: GrantFiled: March 1, 2019Date of Patent: February 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Wang, Kuo-Jung Huang, Yueh-Ching Pai, Huai-Tei Yang
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Patent number: 11569383Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.Type: GrantFiled: June 8, 2020Date of Patent: January 31, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Cheng-Han Lee
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Patent number: 11545363Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: GrantFiled: December 21, 2020Date of Patent: January 3, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
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Patent number: 11527655Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The S/D epitaxial layer includes a first S/D epitaxial layer and a second epitaxial layer. The semiconductor structure includes a gate spacer formed on a sidewall surface of the gate structure, and the gate spacer is directly over the first S/D epitaxial layer. The semiconductor structure includes a dielectric spacer formed adjacent to the gate spacer, and the dielectric spacer is directly over the second epitaxial layer.Type: GrantFiled: January 22, 2021Date of Patent: December 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
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Patent number: 11525185Abstract: Methods and devices are provided wherein rotational gas-flow is generated by vortex generators to decontaminate dirty gas (e.g., gas contaminated by solid particles) in pumping lines of vacuum systems suitable for use at a semiconductor integrated circuit fabrication facility. The vacuum systems use filterless particle decontamination units wherein rotational gas-flow is applied to separate and trap solid particles from gas prior to the gas-flow entering a vacuum pump. Methods are also described whereby solid deposits along portions of pumping lines may be dislodged and removed and portions of pumping lines may be self-cleaning.Type: GrantFiled: September 17, 2019Date of Patent: December 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Fa Wu, Wen-Lung Ho, Huai-Tei Yang
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Patent number: 11526073Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.Type: GrantFiled: March 11, 2022Date of Patent: December 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po Hsuan Li, Yu-Ting Lin, Yun-Yue Lin, Huai-Tei Yang
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Publication number: 20220367632Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.Type: ApplicationFiled: July 25, 2022Publication date: November 17, 2022Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
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Publication number: 20220367715Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Cheng-Han Lee
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Publication number: 20220356567Abstract: Methods and devices are provided wherein rotational gas-flow is generated by vortex generators to decontaminate dirty gas (e.g., gas contaminated by solid particles) in pumping lines of vacuum systems suitable for use at a semiconductor integrated circuit fabrication facility. The vacuum systems use filterless particle decontamination units wherein rotational gas-flow is applied to separate and trap solid particles from gas prior to the gas-flow entering a vacuum pump. Methods are also described whereby solid deposits along portions of pumping lines may be dislodged and removed and portions of pumping lines may be self-cleaning.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Ming-Fa Wu, Wen-Lung Ho, Huai-Tei Yang
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Publication number: 20220352374Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: ApplicationFiled: June 29, 2022Publication date: November 3, 2022Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee