Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.

Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.

Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.

Abstract: The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.

Abstract: A method for cleaning debris and contamination from an etching apparatus is provided. The etching apparatus includes a process chamber, a source of radio frequency power, an electrostatic chuck within the process chamber, a chuck electrode, and a source of DC power connected to the chuck electrode. The method of cleaning includes placing a substrate on a surface of the electrostatic chuck, applying a plasma to the substrate, thereby creating a positively charged surface on the surface of the substrate, applying a negative voltage or a radio frequency pulse to the electrode chuck, thereby making debris particles and/or contaminants from the surface of the electrostatic chuck negatively charged and causing them to attach to the positively charged surface of the substrate, and removing the substrate from the etching apparatus thereby removing the debris particles and/or contaminants from the etching apparatus.

Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.

Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.

Abstract: A method for cleaning debris and contamination from an etching apparatus is provided. The etching apparatus includes a process chamber, a source of radio frequency power, an electrostatic chuck within the process chamber, a chuck electrode, and a source of DC power connected to the chuck electrode. The method of cleaning includes placing a substrate on a surface of the electrostatic chuck, applying a plasma to the substrate, thereby creating a positively charged surface on the surface of the substrate, applying a negative voltage or a radio frequency pulse to the electrode chuck, thereby making debris particles and/or contaminants from the surface of the electrostatic chuck negatively charged and causing them to attach to the positively charged surface of the substrate, and removing the substrate from the etching apparatus thereby removing the debris particles and/or contaminants from the etching apparatus.

Abstract: An extreme ultra-violet (EUV) lithography system includes an EUV source and EUV scanner. A droplet generator provides a droplet stream in the EUV source. A gas shield is configured to surround the droplet stream. When a laser reacts a droplet in the stream EUV radiation and ionized particles are produced. The gas shield can reduce contamination resulting from the ionized particles by conveying the ionized particles to a droplet catcher. Components of the EUV source may be biased with a voltage to repel or attract ionized particles to reduce contamination from the ionized particles.

Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.

Abstract: A method for cleaning debris and contamination from an etching apparatus is provided. The etching apparatus includes a process chamber, a source of radio frequency power, an electrostatic chuck within the process chamber, a chuck electrode, and a source of DC power connected to the chuck electrode. The method of cleaning includes placing a substrate on a surface of the electrostatic chuck, applying a plasma to the substrate, thereby creating a positively charged surface on the surface of the substrate, applying a negative voltage or a radio frequency pulse to the electrode chuck, thereby making debris particles and/or contaminants from the surface of the electrostatic chuck negatively charged and causing them to attach to the positively charged surface of the substrate, and removing the substrate from the etching apparatus thereby removing the debris particles and/or contaminants from the etching apparatus.

Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The S/D epitaxial layer includes a first S/D epitaxial layer and a second epitaxial layer. The semiconductor structure includes a gate spacer formed on a sidewall surface of the gate structure, and the gate spacer is directly over the first S/D epitaxial layer. The semiconductor structure includes a dielectric spacer formed adjacent to the gate spacer, and the dielectric spacer is directly over the second epitaxial layer.

Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.